3D Memory Channel Interface Without Plugs for Faster Programming
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in increasing storage density and electron transfer efficiency due to the complexity of stacked layers and interference from channel plugs during programming operations.
Innovation Solution
The design includes a three-dimensional memory device with stacked layers, a storage channel structure, and a select gate structure, where the first channel layer contacts the second channel layer directly, eliminating the need for channel plugs and improving programming efficiency by optimizing the distance and material properties of the channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If channel plugs are used to connect channel layers, then electrical connection is achieved, but programming interference increases and programming efficiency decreases
Solution Approach 1:
The patent removes the channel plug structure from the memory device architecture. By eliminating the channel plug, the source of programming interference is extracted, allowing for more efficient programming operations while maintaining electrical connection through direct contact between channel layers
2Quantity of substance
If stacked layers are added to increase storage density, then storage capacity improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the function of channel plugs into the channel layers themselves by making the channel layers directly contact each other. This consolidation reduces the number of discrete components needed in the stacked structure, simplifying the overall device complexity while maintaining storage density
Solution Approach 2:
The patent utilizes vertical stacking of channel layers in the third dimension to increase storage density. By arranging channel layers stacked above each other with direct contact, the design achieves high storage capacity without proportionally increasing lateral device footprint or manufacturing complexity
3Speed
If distance between channel layers is reduced to improve electron transfer, then transfer efficiency increases, but manufacturing precision requirements increase
Solution Approach 1:
The channel layers are designed to self-align and contact each other during the manufacturing process. The direct contact configuration allows the layers to naturally position themselves, reducing the need for precise external control of spacing and minimizing manufacturing precision requirements while maintaining optimal electron transfer distance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances storage density and reduces programming interference, allowing for more efficient electron transfer and improved control over memory cells, thereby increasing the reliability and performance of three-dimensional memory devices.
Implementation Method 1
a first end of the first channel layer away from the semiconductor layer contacts a second end of the second channel layer proximate to the semiconductor layer
Data Source
AI summary
The present disclosure provides a three-dimensional memory device and a manufacturing method thereof, the three-dimensional memory device including: a plurality of stacked layers; a storage channel structure vertically penetrating the stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers; and a select channel structure vertically penetrating the select gate structure and comprising a second channel layer; wherein an outer sidewall of the second channel layer is in contact with an inner sidewall of the first channel layer.