3D Memory Device Vertical Channel Pillar Stacking
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Solution Overview
Problem
Three-dimensional (3D) memory devices with vertical channel structures face challenges in increasing memory cell density due to limited area utilization, as existing fabrication processes are complex and inefficient in stacking memory cells vertically.
Innovation Solution
A memory device design featuring a word line, bit line, source line, and channel pillar with a charge storage structure, where the channel pillar penetrates through and is connected to the word line, bit line, and source line, and the charge storage structure surrounds the word line, allowing for increased vertical stacking and simplified fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 3D memory devices with vertical channel structures are used, then storage capacity increases, but fabrication process complexity increases and manufacturing precision deteriorates
Solution Approach 1:
The fabrication process is divided into distinct stages: forming bit lines and source lines in separate layers, creating sacrificial layers at different levels, and sequentially forming charge storage structures and word lines. This segmentation simplifies the overall complex fabrication process by breaking it into manageable, standardized steps that can be repeated for multiple memory cells.
Solution Approach 2:
Sacrificial layers are formed in advance before the channel pillars and charge storage structures are created. These preliminary sacrificial layers define the spatial relationships and dimensions of subsequent structures, enabling precise positioning of word lines and charge storage structures without requiring complex real-time adjustments during fabrication.
2Quantity of substance
If more memory cells are stacked vertically per unit area, then memory cell density increases, but substrate area utilization becomes more difficult to optimize
Solution Approach 1:
The memory structure employs nested arrangements where charge storage structures are positioned between channel pillars, word lines are formed around charge storage structures, and multiple such units are stacked vertically. This nesting maximizes the use of three-dimensional space, allowing more memory cells to be packed into a given substrate area by utilizing vertical stacking rather than only horizontal expansion.
Solution Approach 2:
The invention transitions from two-dimensional planar memory cell arrangements to three-dimensional vertical stacking. By forming multiple layers of bit lines, source lines, channel pillars, and word lines at different heights, the structure achieves higher memory cell density by exploiting the vertical dimension while maintaining efficient substrate area utilization through regular, repeatable unit cell designs.
3Reliability
If channel pillars completely penetrate through bit lines, then connection reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The bit lines are formed completely through the substrate before the channel pillars are created. This preliminary formation establishes precise, pre-defined pathways that guide subsequent channel pillar fabrication. The pre-formed bit lines serve as templates that automatically ensure proper alignment and penetration depth, reducing the precision requirements for later steps while guaranteeing reliable electrical connections.
Solution Approach 2:
Sacrificial layers are used as intermediary structures during fabrication. These temporary layers are formed at specific positions, guide the formation of channel pillars to ensure they penetrate bit lines correctly, and are later removed. The sacrificial layers act as mediators that simplify the alignment process by providing physical references and spacing during manufacturing, ensuring consistent connection reliability without requiring extreme precision.
Data Source
AI summary
A memory device and method of forming the same are provided. The memory device includes a word line, a bit line, a source line, a channel pillar, and a charge storage structure. The bit line and the source line are disposed on opposite sides of the word line in a vertical direction. The channel pillar penetrates through and is connected to the word line, the bit line and the source line. The charge storage structure surrounds a top surface and a bottom surface of the word line and is laterally sandwiched between the channel pillar and the word line. The channel pillar completely penetrates through and is laterally surrounded by the bit line.