3D Memory Channel Replacement for High-Density Cell Reliability
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Solution Overview
Problem
Existing 3D memory devices face challenges in achieving improved performance and reliability due to limitations in their design and fabrication processes.
Innovation Solution
A method for fabricating a semiconductor device that includes forming a cell mold with a dummy channel pattern, creating horizontal and vertical conductive lines, replacing the dummy channel layer with a channel layer, and forming a data storage element, thereby enhancing the integration and performance of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in 3D to increase capacity, then memory density is improved, but performance and reliability deteriorate
Solution Approach 1:
The patent segments the channel layer into multiple discrete channel regions separated by isolation structures, allowing each memory cell to have independent channel control. This segmentation enables better electrical isolation between stacked cells, improving reliability while maintaining high density through vertical stacking.
Solution Approach 2:
The patent applies different material compositions and structural configurations to different regions of the 3D memory device. Specifically, the channel layer has varying cross-sectional shapes and sizes at different vertical levels, and dielectric layers are strategically placed to provide local electrical isolation, optimizing both performance and reliability in each region.
2Quantity of substance
If memory cells are stacked in 3D to increase capacity, then memory density is improved, but performance deteriorates
Solution Approach 1:
The patent transitions from planar 2D memory architecture to 3D vertical stacking, utilizing the vertical dimension to increase memory capacity. Multiple memory cells are stacked along the vertical axis, each with its own channel layer, allowing high density without compromising individual cell performance through maintained horizontal dimensions.
Solution Approach 2:
The channel layer is segmented into distinct regions with controlled dimensions and shapes at different vertical levels. This segmentation allows optimization of channel width and length for each memory cell level, maintaining excellent charge control and low leakage currents that preserve performance while enabling vertical stacking for high density.
3Ease of manufacture
If conventional fabrication processes are used for 3D memory, then manufacturing simplicity is maintained, but integration and performance are limited
Solution Approach 1:
The patent forms the channel layer with specific cross-sectional shapes and dimensions before subsequent processing steps. The dummy channel pattern is initially formed with simplified geometry, then selectively removed to create the final channel structure. This preliminary formation simplifies the overall fabrication by establishing the complex 3D channel architecture early in the process sequence.
Solution Approach 2:
The patent introduces dummy channel patterns as intermediary structures during fabrication. These dummy channels are formed initially to define the cell mold structure, then selectively removed to create the actual channel layers. This intermediary approach simplifies the fabrication process by using a template-based method rather than directly forming complex 3D channels.
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a cell mold including a dummy channel pattern and a plurality of mold layers over a lower structure; forming a horizontal conductive line that intersects with the dummy channel pattern; forming a dummy channel layer by trimming the dummy channel pattern; forming a data storage element that is coupled to a first side of the dummy channel layer; replacing the dummy channel layer with a channel layer; and forming a vertical conductive line that is coupled to a second side of the channel layer.