3D Memory Channel Layer Doping for Resistance Reduction
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Solution Overview
Problem
As the levels of multi-layers stacking structure in 3D NVM flash memory devices increase, the operation current rises, and the channel resistance of memory cells formed on the lower portion of trenches deteriorates due to dimension shrinkage from the etching process, affecting the performance and reliability of the device.
Innovation Solution
A 3D memory device is fabricated with a multi-layers stacking structure that includes a substrate, conductive layers, and insulating layers, featuring a trench with a memory layer on the sidewall and a channel layer divided into upper, lower, and string portions by ion implantation, where the string portion has a doping concentration lower than the upper and lower portions, reducing channel resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the levels of multi-layers stacking structure increase to achieve higher memory density, then the memory capacity is improved, but the operation current increases and channel resistance deteriorates
Solution Approach 1:
The patent applies local quality by creating different doping concentrations in different regions of the channel layer. The string portion has a first doping concentration while the upper and lower portions have a second doping concentration, allowing each region to be optimized for its specific function - the string portion for connectivity and the upper/lower portions for charge storage and control
Solution Approach 2:
The patent changes the doping concentration parameter of the channel layer to resolve the contradiction. By adjusting the doping concentration in different regions (first concentration in string portion, second concentration in upper and lower portions), the channel resistance is reduced while maintaining the high-density multi-layer structure
2Shape
If the etching process is used to form trenches in the multi-layers stacking structure, then the ridge-shaped stacks are formed, but the dimension shrinkage at the bottom of trenches increases channel resistance
Solution Approach 1:
The patent addresses the etching-induced dimension shrinkage by applying local quality through region-specific doping. The string portion of the channel layer, which is most affected by the trench geometry, receives a different doping concentration than the upper and lower portions, compensating for the dimensional changes and reducing channel resistance
Solution Approach 2:
The doping process is performed as a preliminary anti-action to counteract the harmful effects of the etching process. By introducing dopants before final device operation, the channel resistance caused by etching-induced dimension shrinkage is preemptively reduced
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ion implantation process significantly reduces channel resistance, improving the performance and reliability of the 3D memory device by addressing high channel resistance issues caused by increased stacking levels and etching process-induced dimension shrinkage.
Implementation Method 1
an ion implantation process is performed to drive a plurality of dopants into the channel layer, so as to at least divide the channel layer into an upper portion adjacent to an opening of the trench, a lower portion adjacent to a bottom of the trench and a string portion disposed on the sidewall
Data Source
AI summary
A 3D memory device includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a memory layer and a channel layer. The insulating layers are alternately stacked with the conductive layers on the substrate to form a multi-layers stacking structure, wherein the multi-layers stacking structure has at least one trench penetrating through the insulating layers and the conductive layers. The memory layer covers on the multi-layers stacking structure and at least extends onto a sidewall of the trench. The cannel layer covers on the memory layer and includes an upper portion adjacent to an opening of the trench, a lower portion adjacent to a bottom of the trench and a string portion disposed on the sidewall, wherein the string portion connects the upper portion with the lower portion and has a doping concentration substantially lower than that of the upper portion and lower portion.