3D Memory Stack Channel Structure for Reliable Cell Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The operational reliability of three-dimensional semiconductor memory devices is compromised as the number of memory cells stacked over the substrate increases, leading to integration challenges.
Innovation Solution
A semiconductor memory device structure is designed with a doped semiconductor layer extending into a hole, a core insulating pattern, and a channel pattern, along with a spacer pattern to maintain spacing and enhance electrical connectivity, thereby improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells stacked over the substrate is increased to improve integration, then the degree of integration is improved, but the operational reliability is deteriorated
Solution Approach 1:
The memory device is segmented into multiple functional regions including source regions, drain regions, channel regions, and core insulating patterns. This segmentation allows for better electrical isolation and controlled current flow paths, maintaining reliability even as the number of stacked memory cells increases
Solution Approach 2:
Core insulating patterns are introduced as intermediary elements between the channel pattern and the substrate. These intermediaries provide electrical isolation and prevent unwanted current leakage, thereby maintaining operational reliability while enabling higher stacking of memory cells
2Quantity of substance
If the number of memory cells stacked over the substrate is increased to improve integration, then the degree of integration is improved, but integration challenges arise
Solution Approach 1:
The structure employs nested arrangements where memory cells are stacked vertically over the substrate, with each layer containing memory cells, channel patterns, and core insulating patterns. This nesting approach maximizes the use of vertical space, improving integration without proportionally increasing device complexity
Solution Approach 2:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional vertical stacking. By utilizing the vertical dimension, the device achieves higher integration density without significantly complicating the manufacturing process, as the stacking follows a systematic layered structure
3Reliability
If a doped semiconductor layer is formed to enhance electrical conductivity, then turn-on current is increased, but manufacturing precision requirements increase
Solution Approach 1:
The semiconductor layer is doped with different doping types in different regions: first doping type in source regions, second doping type in drain regions, and third doping type (different from first and second) in channel regions. This local quality variation optimizes electrical conductivity and carrier injection efficiency in each specific region, enhancing overall device performance while maintaining manufacturability
Data Source
AI summary
A semiconductor memory device includes: a stack structure including a first interlayer insulating layer, and a plurality of second interlayer insulating layers and a plurality of conductive patterns, which are alternately disposed under the first interlayer insulating layer; a hole penetrating the stack structure; a core insulating pattern, a memory pattern, and a channel pattern, disposed inside the hole; and a doped semiconductor layer disposed over the first interlayer insulating layer, the doped semiconductor layer extending to the inside of the hole.