3D Memory Vertical Channel Segmentation for Electrical Reliability
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration due to the high cost of fine pattern forming technology, which hinders increased data storage capacity and performance.
Innovation Solution
A three-dimensional semiconductor memory device with a vertical channel structure, including a stack structure with ground selection lines, word lines, and string selection lines, and separation structures that enhance electrical characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration is greatly influenced by fine pattern forming technology cost and cannot be increased further
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertical channel structures. The vertical channels extend in the third dimension (depth), allowing memory cells to be stacked vertically rather than arranged only in a planar layout. This dimensional change enables significantly increased integration density and data storage capacity without requiring finer lateral patterning, thus avoiding the cost constraints of advanced lithography while maintaining manufacturing feasibility.
2Productivity
If three-dimensional vertical channel structures are implemented, then integration and data storage capacity increase, but electrical characteristics and reliability may deteriorate
Solution Approach 1:
The patent divides the vertical channel structure into multiple segments separated by separation structures. These separation structures partition the continuous vertical channel into discrete segments, allowing independent control and optimization of electrical characteristics in different regions. This segmentation improves reliability by preventing electrical interference between adjacent memory cells and enabling better control over charge distribution, thus maintaining good electrical characteristics while achieving high integration through the vertical architecture.
Data Source
AI summary
A three-dimensional semiconductor memory device includes: a stack structure including a ground selection line, first word lines, second word lines, and a string selection line, which are sequentially stacked on a substrate; vertical channel structures penetrating the stack structure and arranged to form a plurality of columns; a lower separation structure crossing a lower portion of the stack structure in a first direction and dividing the ground selection line along a second direction intersecting the first direction; and first and second upper separation structures crossing an upper portion of the stack structure in the first direction and dividing the string selection line along the second direction, wherein the lower separation structure and the first upper separation structure are vertically overlapped with one of the columns of the vertical channel structures, and the second upper separation structures are provided between the vertical channel structures.