3D Memory Cell Channel Structure for Data Retention Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration density of two-dimensional non-volatile memory devices is limited, prompting the development of three-dimensional non-volatile memory devices with stacked memory cells, but existing structures and manufacturing methods do not adequately enhance operational reliability and integration density.
Innovation Solution
A semiconductor device with a stacked structure of alternately layered conductive and insulating layers, including insulating pillars, channel patterns, and a memory layer, where the memory layer provides openings to expose the channel patterns or insulating pillars, and a manufacturing method involving the formation of channel structures, openings, and patterning to separate the channel layer into patterns, improving data retention characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional non-volatile memory devices are used, then manufacturing is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacked structure, where memory cells are arranged vertically across multiple layers. This dimensional change enables significantly higher integration density by utilizing the vertical space above the substrate rather than only the planar area, allowing multiple memory cells to be stacked in the third dimension.
2Productivity
If three-dimensional stacked structures are implemented, then integration density improves, but operational reliability deteriorates
Solution Approach 1:
The stacked structure is divided into multiple discrete memory cell layers separated by insulating layers. Each memory cell layer can be independently formed and controlled, allowing for better stress management and reduced interference between adjacent cells. The segmentation into distinct functional layers (conductive layers, insulating layers, memory layers) enables independent optimization of each layer's properties to enhance overall reliability.
Solution Approach 2:
Insulating layers are introduced as intermediary elements between adjacent conductive layers and memory cells. These insulating layers provide electrical isolation and mechanical buffering, preventing direct interaction that could cause reliability issues such as charge leakage or stress-induced failures. The insulating layers act as mediators that maintain proper electrical fields and reduce coupling effects between neighboring cells.
3Productivity
If channel structures are tightly packed, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The channel structures are formed using a preliminary patterning process where sacrificial layers or mandrels are first deposited and patterned to define the channel positions. This preliminary action establishes a precise template that guides subsequent material deposition, ensuring that even tightly packed channels are formed with accurate spacing and alignment. The preliminary structure serves as a reference framework that simplifies the formation of fine-featured channel patterns.
Data Source
AI summary
A semiconductor device includes a stacked structure with conductive layers and insulating layers that are stacked alternately with each other, an insulating pillar passing through the stacked structure, a first channel pattern surrounding a sidewall of the insulating pillar, a second channel pattern surrounding the sidewall of the insulating pillar, a first insulator formed between the first channel pattern and the second channel pattern, and a memory layer surrounding the first channel pattern, the second channel pattern, and the first insulator, the memory layer with a first opening located that is between the first channel pattern and the second channel pattern.