3D Memory Channel Connection Pattern for Stable Vertical Stacking
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Solution Overview
Problem
The existing semiconductor memory devices face challenges in enhancing the degree of integration and stability of three-dimensional memory cell stacking, which affects the manufacturing process and efficiency.
Innovation Solution
The semiconductor memory device incorporates a bit line overlapping with a peripheral circuit layer, interlayer insulating layers and conductive patterns alternately stacked, vertical channels penetrating these layers, and connection patterns to connect the vertical channels, along with source and drain select lines, to improve the arrangement and connection of memory cells, thereby enhancing integration and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the amount of stacking of memory cells is increased to improve the degree of integration, then the number of memory cells per unit area increases, but the manufacturing process stability and efficiency deteriorate
Solution Approach 1:
The memory device is divided into multiple stacks, each containing a specific number of memory cells (e.g., five memory cells per stack). This segmentation allows the manufacturing process to be broken down into manageable units, improving process stability while still achieving high integration through the parallel arrangement of multiple stacks on the substrate.
2Quantity of substance
If more memory cells are stacked vertically to increase integration density, then the number of memory cells per unit area increases, but the manufacturing complexity and difficulty increase
Solution Approach 1:
Multiple memory cells are nested vertically within each stack, with each memory cell containing a channel structure surrounded by gate electrodes. This nesting approach allows high integration density to be achieved through vertical stacking while maintaining manufacturing simplicity by using repetitive, modular structures that can be fabricated using standard semiconductor processing techniques.
Data Source
AI summary
A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes: a bit line overlapping with a peripheral circuit layer; interlayer insulating layers and conductive patterns alternately stacked in a first direction on the bit line; vertical channels connected to the bit line, the vertical channels penetrating the interlayer insulating layers and the conductive patterns, the vertical channels protruding farther in the first direction than the stacked interlayer insulating layers and the conductive patterns; a connection pattern in contact with a portion of each of the vertical channels that protrudes farther in the first direction than the stacked interlayer insulating layers and the conductive patterns, the connection pattern connecting the vertical channels; a source channel in contact with the connection pattern, the source channel extending in the first direction; and a source select line surrounding the source channel.