3D Semiconductor Memory Vertical Channel Width Variation
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Solution Overview
Problem
The manufacturing of low-cost, mass-produced three-dimensional (3D) semiconductor memory devices faces obstacles that affect their reliability, primarily due to the high cost of equipment required for forming minute patterns in two-dimensional (2D) semiconductor devices and the challenges in achieving high integration density.
Innovation Solution
A semiconductor memory device design featuring a stack of gate electrodes on a substrate with a vertical insulating structure and a channel portion, where the channel portion includes a first and second channel pattern, with the second channel pattern having a larger width than the sum of the first and upper channel patterns, and a curved or angular profile, enhancing integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional (2D) or planar semiconductor memory devices are used, then the manufacturing process is simpler, but the integration density is limited by the area occupied by unit memory cells
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertical structures by forming gate electrodes and channel structures that extend in the vertical direction through the substrate. This dimensional change allows memory cells to be stacked vertically, dramatically increasing integration density without proportionally increasing the substrate area occupied by each unit memory cell.
2Quantity of substance
If three-dimensional (3D) semiconductor devices are used, then the integration density increases, but manufacturing obstacles arise that affect reliability
Solution Approach 1:
The patent implements varying channel widths at different vertical positions within the 3D structure. The channel structure has a first channel width at an upper portion and a second channel width at a lower portion, with the second width being greater than the first. This local variation in geometry allows optimization of electrical characteristics at different locations, improving threshold voltage control and reducing channel disconnection risks in the 3D structure.
3Manufacturing precision
If equipment for forming minute patterns is used, then the pattern precision improves, but the manufacturing cost increases
Solution Approach 1:
The patent forms three-dimensional structures with varying cross-sectional dimensions at different heights, creating complex vertical patterns that extend through the substrate. This approach increases the effective patterning area and functional density without requiring proportionally higher precision equipment, as the vertical dimension provides additional space for structure formation.
Data Source
AI summary
A semiconductor memory device includes a stack including gate electrodes sequentially stacked on a substrate, a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes, a vertical channel portion disposed on an inner side surface of the vertical insulating structure, and a common source region formed in the substrate and spaced apart from the vertical channel portion. A bottom region of the vertical channel portion has a protruding surface in contact with a bottom region of the vertical insulating structure.