3D Memory Charge Dispersion for Retention
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Solution Overview
Problem
In three-dimensional (3D) semiconductor devices, charge trapped in memory cells can move unevenly due to density differences, affecting programming efficiency and retention characteristics.
Innovation Solution
A programming method that applies a programming voltage to a selected word line to trap charge, then disperses a portion of the trapped charge between adjacent memory cells using sub-voltages applied to adjacent word lines, with verification voltages ensuring the charge is evenly distributed, repeated until the memory cells meet verification criteria.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge is trapped in a selected memory cell by applying programming voltage to a selected word line, then the memory cell is programmed, but charge may move to upper or lower portions due to density differences affecting retention characteristics
Solution Approach 1:
The patent applies preliminary actions by dispersing charge to adjacent memory cells immediately after programming the selected memory cell. By proactively moving charge to neighboring cells before significant density-driven migration occurs, the invention prevents non-uniform charge distribution and maintains reliable retention characteristics in the 3D vertical memory structure.
2Productivity
If charge is trapped in the charge storage film vertically along the tunnel insulating film, then memory cells can be programmed, but trapped charge may move unevenly affecting programming efficiency
Solution Approach 1:
The patent applies local quality by selectively dispersing charge to specific adjacent memory cells (upper and/or lower) based on the selected word line position. Instead of uniform treatment, the invention tailors charge distribution to local requirements, improving programming efficiency while maintaining precise control over charge placement in the vertical 3D structure.
Solution Approach 2:
The invention changes parameters by applying different voltages to different word lines during the programming process. By adjusting voltage levels and application timing to selected versus adjacent word lines, the patent achieves precise control over charge trapping and dispersion, optimizing both programming efficiency and charge distribution accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the retention characteristics and reliability of 3D semiconductor devices by minimizing charge movement and ensuring consistent threshold voltages across memory cells.
Implementation Method 1
programming a selected memory cell by applying a programming voltage to a selected word line electrically coupled to the selected memory cell so that charge is trapped in the selected memory cell
Implementation Method 2
dispersing at least a portion of the charge trapped in the selected memory cell between memory cells adjacent to the selected memory cell by applying a first sub-voltage to adjacent word lines electrically coupled to the adjacent memory cells
Data Source
AI summary
A semiconductor device includes a plurality of electrically coupled memory cells in a generally vertical configuration extending in a generally perpendicular direction from a semiconductor substrate, a peripheral circuit configured to program the memory cells, and a control circuit configured to program a memory cell selected from the plurality of memory cells to trap charge in the selected memory cell, and to issue at least one command to the peripheral circuit to manage a dispersion of at least a portion of the trapped charge between memory cells adjacent to the selected memory cell.