3D Memory Chip Bonding to Shorten Bit-Line Interconnects
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Solution Overview
Problem
Existing three-dimensional memory devices face challenges with increased bit line capacity and operation speed due to long bit lines, which are exacerbated by the need for deep contacts and fine interconnection layers under the memory array, leading to potential increases in chip area and operational delays.
Innovation Solution
The semiconductor memory device integrates an array chip with three-dimensionally disposed memory cells and a circuit chip, where the array chip is bonded to the circuit chip via bonding metals, eliminating the need for deep contacts and reducing interconnect lengths by directly connecting bit lines and word lines to the circuit chip, thus minimizing chip area and operation delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If bit lines are extended under the memory array to connect to transistors, then the control circuit can be integrated under the array, but the bit line length increases causing increased bit line capacity and reduced operation speed
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional vertical interconnection by forming contact holes through the memory array and using bit line extension layers that extend vertically downward. This allows direct connection between bit lines and control circuit transistors without requiring long lateral bit line extensions, thereby reducing bit line capacity while enabling control circuit integration.
2Reliability
If deep contact holes are formed to connect bit lines under the array, then direct connection is achieved, but the chip area increases and manufacturing complexity increases
Solution Approach 1:
The contact holes are formed within the existing memory array structure, nesting the interconnection path within the vertical space already occupied by the memory cells. This eliminates the need for additional lateral space for deep contacts, as the contact holes utilize the vertical dimension within the array footprint rather than requiring extra chip area.
3Ease of manufacture
If fine interconnection layers are provided under the memory array, then bit lines can be connected to transistors, but the manufacturing precision requirements increase
Solution Approach 1:
The bit line extension layers are formed as part of the memory array fabrication process before the control circuit is completed. The contact holes are formed through the array structure in advance, and the bit line extension layers are deposited and patterned to align with these pre-formed contact holes. This preliminary formation of interconnection structures simplifies subsequent manufacturing steps and reduces the precision requirements for final alignment.
Data Source
AI summary
According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.