3D Semiconductor Memory Chip Bonding for Higher Density
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Solution Overview
Problem
The integration of two-dimensional or planar semiconductor memory devices is limited by the cost of advanced pattern forming equipment, making it challenging to increase integration density while maintaining affordability.
Innovation Solution
A semiconductor memory device design that includes a first and second semiconductor chip with a cell array region and a peripheral circuit region, where the cell array region features electrodes stacked on a body conductive layer with vertical structures connected to it, and the peripheral circuit region includes a residual substrate thicker than the body conductive layer, allowing for bonding of the chips with their body conductive layers facing each other, thereby simplifying the fabrication process and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional or planar semiconductor memory devices use advanced pattern forming technologies to increase integration, then integration density is improved, but capital expenditures for process equipment become extremely expensive
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertically stacked structures. Multiple memory cell layers are stacked vertically with body conductive layers positioned between them, enabling increased integration density without requiring advanced pattern forming equipment. This dimensional change allows conventional manufacturing processes to achieve higher integration levels.
Solution Approach 2:
The memory device is divided into multiple discrete memory cell layers stacked vertically, with each layer containing electrodes and body conductive layers. This segmentation allows independent fabrication and stacking of layers using conventional processes, avoiding the need for single-step high-precision patterning while achieving high integration through vertical assembly.
2Device complexity
If the body conductive layer thickness is reduced to simplify fabrication and reduce device thickness, then manufacturing complexity is decreased, but electrical connection reliability may be compromised
Solution Approach 1:
The body conductive layer is formed as a composite structure combining multiple materials including polysilicon, metal layers (such as tungsten, copper, or aluminum), and conductive oxides. This composite construction maintains electrical conductivity and connection reliability even when the overall layer thickness is reduced, while enabling simplified fabrication processes through sequential deposition of each material layer.
Solution Approach 2:
The patent optimizes the thickness and material composition parameters of the body conductive layer to achieve a balance between electrical performance and fabrication simplicity. By controlling the thickness within specific ranges and selecting appropriate conductive materials, the device achieves reliable electrical connections with reduced overall thickness and simplified manufacturing.
Data Source
AI summary
A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.