3D Memory Chip Bonding Structure for Shorter Bit-Line Routing
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Solution Overview
Problem
Existing three-dimensional semiconductor memory devices face challenges in reducing the space factor of control circuits within the chip, managing long bit lines that affect capacity and speed, and integrating control circuits under the memory array without compromising reliability and heat resistance.
Innovation Solution
The semiconductor memory device comprises an array chip with a three-dimensionally disposed memory cell array and a circuit chip with a control circuit, where the two chips are bonded together with bonding metals, eliminating the need for a substrate in the array chip and allowing direct connection of bit lines and interconnection layers to the circuit chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If control circuit is provided under the memory array to reduce space factor, then chip area is reduced, but heat resistance and reliability are compromised
Solution Approach 1:
The device is divided into two separate chips: a first chip containing the memory cell array and a second chip containing the control circuit. This segmentation allows each chip to be optimized independently for its specific function, with the memory chip focusing on storage density and the control chip focusing on processing capability and heat dissipation, thereby resolving the conflict between area reduction and heat resistance.
Solution Approach 2:
A bonding substrate is introduced as an intermediary component between the memory chip and control chip. This bonding substrate serves as a mediator that facilitates electrical connection and mechanical bonding while providing a platform for heat dissipation from the control chip, thus maintaining reliability while enabling compact integration.
2Adaptability or versatility
If bit lines are extended under the array to connect control circuit, then control circuit integration is achieved, but bit line length increases affecting capacity and speed
Solution Approach 1:
The bit line connection path is segmented into two parts: a first bit line extending from the memory cell array to the bonding substrate, and a second bit line extending from the bonding substrate to the control circuit. This segmentation shortens the bit line length on the memory chip, reducing capacitance and improving operation speed while still achieving control circuit integration.
Solution Approach 2:
The bonding substrate acts as an intermediary that provides connection points for both the first bit line from the memory array and the second bit line to the control circuit. This intermediary structure enables efficient signal transmission by minimizing the length of bit lines on the memory chip, thereby improving operation speed while maintaining integration capability.
3Adaptability or versatility
If deep contact is formed to connect under-array interconnection, then control circuit connection is achieved, but additional space and complexity are required
Solution Approach 1:
The complex deep contact formation process is extracted from the memory chip fabrication and transferred to the bonding substrate fabrication process. The bonding substrate provides pre-formed contact structures that simplify the overall device manufacturing by eliminating the need to form deep contacts through the memory chip substrate, thereby reducing device complexity while achieving under-array connection.
Solution Approach 2:
The bonding substrate serves as an intermediary that provides a platform for forming connection structures without requiring deep contact formation in the memory chip. This intermediary approach simplifies the contact formation process by performing connections at the bonding substrate level rather than requiring complex through-substrate vias in the memory chip, thus reducing device complexity.
Data Source
AI summary
According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.