3D Memory Chip Bonding with Test Cell Array for Reliable Integration
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Solution Overview
Problem
The challenge of achieving high-capacity and high-integration in memory devices, particularly in 3D memory cell arrays, is addressed by integrating a 3D memory cell array with a peripheral circuit chip, where the peripheral circuit chip includes a 2D test cell array and a peripheral circuit, enabling efficient electrical operation and data management.
Innovation Solution
A memory device comprising a memory chip with a 3D cell array and a peripheral circuit chip with a 2D test cell array, where the chips are bonded through word and bit line bonding pads, allowing for electrical die sorting and information data reading to ensure proper functioning and initialization of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a 3D memory cell array is integrated with a peripheral circuit chip to achieve high capacity and high integration, then the storage capacity and integration density are improved, but the manufacturing complexity and electrical connection reliability may deteriorate
Solution Approach 1:
The memory device is divided into separate memory chip and peripheral circuit chip components, each fabricated independently using optimized processes (3D cell array fabrication for memory chip, 2D cell array and peripheral circuit fabrication for peripheral circuit chip). This segmentation allows specialized manufacturing processes for each component while maintaining overall system integration through subsequent bonding operations.
2Quantity of substance
If a 3D memory cell array is integrated with a peripheral circuit chip to achieve high capacity and high integration, then the storage capacity and integration density are improved, but the manufacturing complexity and electrical connection reliability may deteriorate
Solution Approach 1:
Electrical die sorting (EDS) is performed on the peripheral circuit chip before bonding to the memory chip. This preliminary electrical testing identifies and eliminates defective peripheral circuit chips, ensuring that only functional chips proceed to the bonding process. This advance quality control measure prevents potential reliability issues from propagating through the final integrated device.
3Reliability
If electrical die sorting is performed on the peripheral circuit chip before bonding, then the reliability of the final device is improved, but the manufacturing time and process complexity may worsen
Solution Approach 1:
The electrical die sorting process is implemented as a preliminary screening step performed on peripheral circuit chips before they are bonded to memory chips. By conducting this electrical testing and validation early in the manufacturing sequence, defective chips are identified and removed from the production stream before committing to the irreversible bonding process, thereby preventing rework and ensuring high yield of functional integrated devices.
Data Source
AI summary
A memory device includes a memory chip including a memory cell array connected to first word lines and first bit lines, first word line bonding pads respectively connected to the first word lines, and first bit line bonding pads respectively connected to the first bit lines, and a peripheral circuit chip, wherein the peripheral circuit chip includes a test cell array connected to second word lines and second bit lines, second word line bonding pads respectively connected to the first word line bonding pads, second bit line bonding pads respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines or the second bit line bonding pads and the second bit lines.