3D Memory Chip Assembly via Surface-Activated Bonding
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Solution Overview
Problem
The manufacturing of three-dimensional NAND flash memory devices faces challenges in reducing memory opening pitch and increasing word line density, leading to complexity in etch and metal replacement processes, and the thermal budget used in CMOS processes affects CMOS device performance, particularly for CMOS-under-array peripheral circuits.
Innovation Solution
The solution involves forming through-substrate via structures in a replacement-scheme process integration, where CMOS and memory chips are separately fabricated on different substrates and bonded using surface-activated bonding, allowing for independent thermal processing and reducing thermal impact on CMOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory opening pitch is reduced and word line density is increased to achieve high density at lower cost, then storage capacity is improved, but etch process complexity and metal replacement process complexity increase
Solution Approach 1:
The patent divides the memory device into multiple tiers stacked vertically, with each tier containing a complete set of memory openings, word lines, and bit lines. This segmentation allows the complex high-density storage to be achieved through vertical stacking rather than increasing lateral density, thereby reducing the complexity of individual etch processes while maintaining high storage capacity.
Solution Approach 2:
The patent transitions from two-dimensional lateral expansion to three-dimensional vertical stacking by forming multiple tiers of memory structures stacked along the vertical direction. This dimensional change enables high storage density without requiring further reduction in memory opening pitch, thus avoiding the associated increase in etch process complexity.
2Quantity of substance
If memory opening pitch is reduced and word line density is increased to achieve high density at lower cost, then storage capacity is improved, but metal replacement process complexity increases
Solution Approach 1:
The patent segments the metal interconnect structure into multiple tiers, with each tier having its own set of word lines and bit lines formed through independent metal replacement processes. This segmentation allows each tier's metal formation to be handled separately, reducing the overall complexity of the metal replacement process while achieving high storage capacity through vertical integration.
Solution Approach 2:
By stacking multiple tiers vertically, the patent distributes the metal replacement operations across different vertical levels rather than requiring all metal structures to be formed in a single complex lateral process. This dimensional approach simplifies each individual metal replacement step while achieving high storage density through vertical stacking.
3Quantity of substance
If multi-tier structures are used for three-dimensional NAND memory devices, then storage capacity is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent divides the multi-tier memory structure into modular units, where each tier can be formed through a standardized set of processing steps that are then repeated for additional tiers. This modular segmentation reduces manufacturing process complexity by creating a repeatable fabrication sequence rather than requiring entirely new processes for each additional tier.
Solution Approach 2:
The patent performs preliminary actions such as forming sacrificial structures, creating alternating stacks of insulating and conductive layers, and preparing substrate surfaces before the actual tier formation. These preliminary steps establish a foundation that simplifies subsequent tier fabrication, reducing overall manufacturing complexity while enabling high storage capacity through multi-tier stacking.
4Adaptability or versatility
If CMOS and memory chips are fabricated together on the same substrate, then integration is improved, but thermal budget constraints degrade CMOS device performance
Solution Approach 1:
The patent physically segments the CMOS chip and memory chip into separate substrates, allowing each to be optimized and processed independently. The CMOS chip can undergo high-temperature processing without affecting memory structures, while the memory chip can be processed according to its own thermal requirements. This segmentation maintains integration through separate bonding while eliminating thermal budget conflicts that would otherwise degrade CMOS performance.
Solution Approach 2:
The patent uses an intermediary bonding interface to connect the separately processed CMOS chip and memory chip. This intermediary connection allows both chips to be fabricated independently under their respective optimal thermal conditions, then joined together to achieve integration without the thermal budget constraints that would arise from co-fabrication on a single substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, improves wafer chip yield, and minimizes thermal budget constraints, enabling efficient integration of CMOS and three-dimensional NAND memory devices without degrading CMOS performance.
Implementation Method 1
bonded using surface-activated bonding
Data Source
AI summary
Sacrificial pillar structures are formed through a first semiconductor substrate on which first semiconductor devices are subsequently formed. After backside thinning of the first semiconductor substrate, the sacrificial pillar structures are replaced with integrated through-substrate via and pad structures to provide a first semiconductor chip. A second semiconductor chip is provided, which includes a second semiconductor substrate, second semiconductor devices, and second bonding pad structures electrically connected to a respective one of the second semiconductor devices. The first bonding pad structures are bonded to a respective one of the second bonding pad structures by surface activated bonding.