3D Memory Peripheral Circuit Stacking for Smaller Chip Footprint
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Solution Overview
Problem
As the number of layers of word lines in 3D nonvolatile memory devices increases, the cell area required to maintain capacity is reduced, but the area needed for peripheral circuits decreases at a slower rate, limiting the reduction in chip size.
Innovation Solution
A memory device is designed with a peripheral circuit implemented across multiple chips stacked vertically, including high-voltage and low-voltage transistor circuits in separate chips to optimize space and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the number of layers of word lines is increased to reduce cell area, then memory capacity density is improved, but the area required for peripheral circuits decreases at a slower rate, limiting overall chip size reduction
Solution Approach 1:
The patent applies three-dimensional stacking of multiple chips vertically to implement peripheral circuits. By transitioning from a two-dimensional layout to a three-dimensional structure, the peripheral circuits are distributed across multiple stacked chips, thereby reducing the planar area occupied by peripheral circuits on each individual chip while maintaining overall functionality.
Solution Approach 2:
The peripheral circuit is divided and segmented across multiple chips. Specifically, different functional blocks of the peripheral circuit are implemented on different stacked chips, allowing the total peripheral circuit area to be distributed in the vertical dimension rather than concentrated in the planar dimension.
2Reliability
If high-voltage transistors are implemented with sufficient width and length to ensure performance, then transistor reliability is improved, but the area occupied by the peripheral circuit increases
Solution Approach 1:
By stacking multiple chips vertically, the patent provides sufficient area for high-voltage transistors to achieve required performance specifications without increasing the planar footprint. The vertical stacking allows large transistors to be accommodated in the third dimension while maintaining a compact two-dimensional profile.
Solution Approach 2:
The peripheral circuit implementing high-voltage transistors is segmented and distributed across multiple stacked chips. This segmentation allows each chip to contain optimized transistor implementations with sufficient dimensions for reliable operation, while the overall circuit area is managed through vertical distribution.
Data Source
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AI summary
A memory device (1000A) is provided. The memory device includes: a memory cell array (1100) implemented in a first chip (Chip 1); and a peripheral circuit (1200) implemented in a second chip (Chip 2) and a third chip (Chip 3) which overlaps the first chip (Chip 1) along a vertical direction. The peripheral circuit (1200) includes: a first peripheral circuit (11_1) implemented in the second chip (Chip 2) and the third chip (Chip 3); a second peripheral circuit (11_2) implemented in the second chip (Chip 2) and including at least one high-voltage transistor; and a third peripheral circuit (11_3) implemented in the third chip (Chip 3) and including at least one low-voltage transistor. The first peripheral circuit (11_1) includes: a first sub-peripheral circuit (11_1a) implemented in the second chip (Chip 2) and including at least one high-voltage transistor; and a second sub-peripheral circuit (11_1b) implemented in the third chip (Chip 3) and including at least one low-voltage transistor.