3D Memory Interconnect Layout for Integrated CMOS Peripheral Circuits
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Solution Overview
Problem
Existing memory devices with three-dimensional memory structures face challenges in integrating peripheral circuits efficiently, leading to increased complexity and potential performance bottlenecks.
Innovation Solution
A memory device configuration that integrates a memory chip with a CMOS chip, utilizing a stacked interconnect structure and conductor layers to facilitate efficient communication between memory cells and peripheral circuits, enhancing data storage and retrieval operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory structure is used to increase capacity and integration, then storage capacity is improved, but device complexity increases due to separate memory chip and CMOS chip bonding
Solution Approach 1:
The patent merges the memory chip and CMOS chip into a single integrated structure where peripheral circuits are formed directly on the same substrate as the memory cell array. This eliminates the need for separate chip bonding while maintaining high storage capacity through three-dimensional stacking of memory cells, thereby reducing device complexity.
Solution Approach 2:
The patent extends the interconnect structure into the vertical dimension by forming bit line extenders that protrude from the main body of the memory device. This three-dimensional interconnect architecture allows peripheral circuits to be integrated on the same chip while maintaining efficient electrical connections, resolving the complexity issue associated with planar two-dimensional layouts.
2Ease of manufacture
If separate chips are used for memory structure and peripheral circuits, then manufacturing is simplified, but integration efficiency deteriorates
Solution Approach 1:
The patent segments the memory device into distinct functional regions: a memory cell array region and a peripheral circuit region, both formed on the same substrate. This segmentation allows each region to be optimized independently while maintaining efficient integration, achieving both ease of manufacture and high integration efficiency.
Solution Approach 2:
The substrate serves multiple functions simultaneously: it acts as the base for both the memory cell array and the peripheral circuits, and provides the foundation for the three-dimensional interconnect structure. This multi-functional substrate design enables efficient integration while simplifying the manufacturing process compared to multi-chip solutions.
3Quantity of substance
If three-dimensional memory structure is implemented, then capacity increases, but interconnect complexity increases
Solution Approach 1:
The patent introduces vertical dimensionality to the interconnect architecture by forming bit line extenders that protrude from the main body. This three-dimensional interconnect structure efficiently connects the vertically stacked memory cells to peripheral circuits without requiring complex lateral routing, thereby managing interconnect complexity despite increased capacity.
Solution Approach 2:
The bit line extenders act as intermediary structures that bridge the memory cell array region and the peripheral circuit region. These extenders simplify the interconnection by providing direct vertical access points, reducing the complexity of routing signals between the three-dimensional memory structure and peripheral circuits.
Data Source
AI summary
A memory device includes a substrate; first conductors aligned apart from each other in a first direction; a second conductor and a third conductor each extending in a second direction between the substrate and the first conductors, and being aligned apart from each other in the second direction; fourth conductors aligned apart from each other in the first direction on an opposite side of the substrate with respect to the first conductors; a fifth conductor extending in the second direction between the first conductors and the fourth conductors; and a first interconnect coupling between the fifth conductor and the substrate. The first interconnect includes a contact extending in the first direction and passing through the first conductors between the second and third conductors.