3D Memory Array Layout With Split CMOS Control Logic
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Solution Overview
Problem
Microelectronic device designers face challenges in increasing integration density and performance while managing the size and complexity of control logic devices within memory devices, which often consume more real estate and impede memory density and performance improvements.
Innovation Solution
The implementation of a microelectronic device structure comprising a first and second CMOS region, with control logic devices positioned to enhance data transfer speeds and increase memory cell density by reducing electrical connection paths and optimizing the arrangement of control logic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If control logic devices are positioned in conventional locations within the memory device, then the device structure is simple to manufacture, but the memory cell density and data transfer speeds are limited
Solution Approach 1:
The patent positions control logic devices in three-dimensional space above and below the memory array, utilizing vertical dimensionality rather than only lateral placement. This allows control logic to be distributed across multiple levels, increasing memory cell density without complicating the manufacturing process, as each level can be formed using standard semiconductor fabrication techniques.
Solution Approach 2:
The control logic functionality is segmented into multiple separate control logic devices distributed across different locations and levels. Rather than using a single centralized control logic unit, the patent divides control functions among multiple devices, allowing parallel operation and improved data transfer speeds while maintaining manufacturing simplicity through modular device placement.
2Speed
If control logic devices are positioned to enhance data transfer speeds by reducing electrical connection paths, then data transfer performance improves, but the device structure becomes more complex
Solution Approach 1:
The patent reduces electrical connection paths by transitioning from lateral connections to vertical connections through the memory array. Control logic devices positioned above or below the memory array can connect to memory cells through shorter vertical pathways, significantly improving data transfer speeds. The electrical connection configuration remains relatively simple as it utilizes standard vertical interconnect structures already present in three-dimensional memory architectures.
3Speed
If the quantity and arrangement of control logic devices are increased to improve performance, then data transfer speeds increase, but the horizontal footprint of the memory device increases
Solution Approach 1:
The patent moves control logic devices from the horizontal plane to vertical levels above and below the memory array. This dimensional transition allows multiple control logic devices to be stacked in the vertical direction, enabling increased data transfer performance through parallel operations while maintaining a compact horizontal footprint. The memory device effectively utilizes three-dimensional space rather than being constrained to two-dimensional layout.
Solution Approach 2:
The patent nests control logic devices within the vertical structure of the memory device, positioning them in available spaces above or below the memory array. This nesting approach allows control logic functionality to be integrated into the existing memory device structure without requiring additional horizontal area, as control logic devices are embedded within the vertical architecture rather than occupying lateral space.
Data Source
AI summary
A microelectronic device comprises a first control logic region comprising first control logic devices and a memory array region vertically overlying the first control logic region. The memory array region comprises capacitors, access devices laterally neighboring and in electrical communication with the capacitors, conductive lines operatively associated with the access devices and extending in a lateral direction, and first conductive pillars operatively associated with the access devices and vertically extending through the memory array region. The microelectronic device further comprises a second control logic region comprising second control logic devices vertically overlying the memory array region. Related microelectronic devices, memory devices, electronic systems, and methods are also described.