3D Memory Array Layout With CMOS Drivers Over Staircase Region
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Solution Overview
Problem
Microelectronic device designs face challenges in reducing feature dimensions and separation distances to increase integration density while maintaining performance and simplifying designs, particularly due to processing conditions and the complexity of control logic devices in memory devices.
Innovation Solution
A microelectronic device structure comprising a multiplexer region with transistor structures, vertically stacked memory cells, and conductive pillar structures that facilitate reduced distances between control logic devices and memory arrays, allowing for increased operating speed and reduced footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control logic devices are integrated within the base control logic structure underlying the memory array, then memory device performance is improved, but the processing conditions (temperatures, pressures, materials) for forming the memory array limit the configurations and performance of the control logic devices
Solution Approach 1:
The patent divides the microelectronic device into separate structures: a first microelectronic device structure containing the memory array, and a second microelectronic device structure containing the control logic devices. These structures are formed independently and then coupled together, allowing each to be optimized separately without processing condition conflicts.
Solution Approach 2:
The patent introduces conductive pillar structures and interconnect structures as intermediaries to couple the separately formed memory array structure and control logic structure. This intermediary coupling mechanism enables the two structures to be formed under different processing conditions and then integrated functionality.
2Quantity of substance
If the quantities, dimensions, and arrangements of control logic devices are increased to handle higher memory array density, then memory array capacity is improved, but the control logic devices consume more real estate, reducing the memory density of the memory device
Solution Approach 1:
The patent transitions from a two-dimensional planar integration approach to a three-dimensional vertical stacking approach. The control logic devices are placed in a separate structure that is coupled to the memory array structure, utilizing the vertical dimension rather than consuming horizontal real estate. This allows high-density memory arrays to be achieved without proportionally increasing the footprint of control logic devices.
3Quantity of substance
If feature dimensions and separation distances are reduced to increase integration density, then manufacturing complexity increases due to processing condition constraints
Solution Approach 1:
The patent segments the fabrication process into separate formation steps for the memory array structure and control logic structure. Each structure can be manufactured independently under optimized processing conditions, avoiding the need to simultaneously satisfy conflicting processing requirements for high-density integration.
Data Source
AI summary
A microelectronic device comprises a first microelectronic device structure comprising a stack structure comprising conductive structures vertically alternating with insulative structures, a staircase structure within the stack structure, and vertical stacks of memory cells. Each vertical stack of memory cells individually comprises a vertical stack of capacitor structures, transistor structures each individually neighboring a capacitor structure of the capacitor structures, and a conductive pillar structure vertically extending through the transistor structures. The microelectronic device further comprises a second microelectronic device structure attached to the first microelectronic device structure, the second microelectronic device structure comprising a sub word line driver region comprising complementary metal-oxide-semiconductor (CMOS) circuits vertically overlying and within a horizontal area of the staircase structure, and conductive contact structures vertically extending between steps of the staircase structure and the sub word line driver region. Related memory devices, electronic systems, and methods are also described.