3D Memory Channel and Gate Slit Co-Etching for Higher Yield
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Solution Overview
Problem
The fabrication of three-dimensional memory devices faces challenges due to high costs and yield loss caused by the increasing aspect ratios of channel holes and gate line slit trenches, leading to tilting and interference issues during the etching process, which complicates the development of more memory layers.
Innovation Solution
A method is introduced where channel holes and gate line slit trenches are formed simultaneously using dummy channel holes, allowing for one-time etching and reducing the risk of tilting and interference, thereby lowering fabrication costs and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If channel holes and gate line slit trenches are formed separately through multiple etching processes, then the fabrication process can be more controlled, but the aspect ratio increases leading to tilting and interference issues
Solution Approach 1:
The patent combines the formation of channel holes and gate line slit trenches into a single etching process by introducing dummy channel holes that serve dual purposes: defining channel hole positions and defining gate line slit trench positions. This merging approach reduces the number of separate etching steps, lowers the cumulative aspect ratio, and prevents tilting and interference issues that arise from multiple sequential etching processes.
Solution Approach 2:
The dummy channel holes act as an intermediary structure that mediates between the channel hole formation and gate line slit trench formation. These dummy holes are filled with sacrificial material that is later removed, allowing both the channel holes and gate line slit trenches to be formed simultaneously without direct interference, thus maintaining structural stability.
2Manufacturing precision
If multiple etching processes are used to form channel holes and gate line slit trenches, then each structure can be optimized independently, but the fabrication cost and complexity increase
Solution Approach 1:
The patent merges multiple fabrication processes into a single etching step by using dummy channel holes as a unified patterning template. This reduces fabrication process complexity from multiple sequential etching steps to one simultaneous etching process, while still allowing independent optimization of channel hole and gate line slit trench dimensions through appropriate dummy hole design.
Solution Approach 2:
The dummy channel holes serve multiple functions simultaneously: they define the positions and dimensions of channel holes, define the positions and dimensions of gate line slit trenches, and provide a unified patterning template for the etching process. This multi-functionality reduces overall process complexity while maintaining optimization capabilities.
3Quantity of substance
If the number of memory layers is increased to improve storage density, then the storage capacity increases, but the aspect ratio of etched structures increases leading to higher yield loss
Solution Approach 1:
The patent applies the merged etching approach to multi-layer memory structures, where dummy channel holes are used to simultaneously define channel holes and gate line slit trenches across multiple layers in a single etching process. This reduces the cumulative aspect ratio that would result from multiple sequential etching steps, thereby maintaining etching precision even as the number of memory layers increases to improve storage density.
4Manufacturing precision
If separate etching processes are used for channel holes and gate line slit trenches, then each structure can be formed with optimal parameters, but tilting and interference occur reducing yield
Solution Approach 1:
The patent combines the formation of channel holes and gate line slit trenches into a single etching process using dummy channel holes as a unified template. This merging eliminates the tilting and interference problems that arise from separate etching processes, as both structures are formed simultaneously with consistent process parameters, thereby improving fabrication yield while maintaining structural optimization.
Data Source
AI summary
Examples of the present application disclose a semiconductor device and a fabrication method thereof and a memory system. The semiconductor device includes: a stack structure including first regions and second regions; channel structures that are located in the first regions and penetrate through the stack structure along a first direction; and gate line isolation structures that are located in the second regions and extend along a second direction, wherein the gate line isolation structures penetrate through the stack structure along the first direction and are in a concavo-convex shape along a third direction.