3D Memory Common-Connection Layout for Speed and Data Retention
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Solution Overview
Problem
Current memory devices face challenges in balancing speed and data retention, with volatile memory devices losing data when power is off and non-volatile devices being slower than needed for modern electronic demands.
Innovation Solution
A three-dimensional memory device is developed using ferroelectric memory cells formed across multiple tiers over a substrate, with a specific structure that includes a semiconductor channel layer, ferroelectric layer, and conductive structures, allowing for efficient data storage and retrieval while sharing select lines to reduce fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If non-volatile memory devices are used to retain data after power off, then data retention is improved, but access speed deteriorates
Solution Approach 1:
The memory device is divided into multiple tiers (first tier and second tier) with different memory cell structures. The first tier uses memory cells with first select lines for fast access, while the second tier uses memory cells with shared select lines for data retention. This segmentation allows the system to achieve both fast access and data retention by operating different tiers according to different requirements.
2Ease of operation
If separate select lines are provided for each memory string, then memory access control is improved, but device complexity and fabrication cost worsen
Solution Approach 1:
The patent merges the select lines by providing a common second select line that is shared by multiple memory strings in the second tier. This reduces the total number of select lines required, simplifying the device structure and reducing fabrication complexity while maintaining the ability to control memory access through the first select lines in the first tier.
3Measurement precision
If more select lines are provided for better memory control, then memory access precision is improved, but fabrication cost worsens
Solution Approach 1:
The patent introduces a tiered vertical structure with two distinct memory tiers, each handling different aspects of memory control. The first tier provides precise access control through dedicated select lines, while the second tier uses shared select lines to reduce fabrication complexity. This dimensional organization allows the system to achieve both precision and cost-effectiveness.
Data Source
AI summary
One aspect of this description relates to a semiconductor device. In some embodiments, the semiconductor device includes a first drain/source structure extending in a first direction, a second drain/source structure extending the first direction and spaced from the first drain/source structure in a second direction perpendicular to the first direction, a third drain/source structure extending in the first direction and spaced from the second drain/source structure in the second direction, a first bit line disposed over the first drain/source structure in the first direction, a common select line that includes a portion disposed over the second drain/source structure in the first direction, a second bit line disposed over the third drain/source structure in the first direction, and a charge storage layer coupled to at least a first sidewall of each of the first drain/source structure, the second drain/source structure, and the third drain/source structure.