3D Memory In-Memory Computation Circuit
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Solution Overview
Problem
Conventional 3D memory devices face limitations in array efficiency, die size, and high cost due to large peripheral circuits formed outside the memory array, leading to poor input/output (I/O) speed and high resource utilization for external data processing, which burdens the I/O interface and limits overall throughput.
Innovation Solution
Incorporating an on-die data processing circuit within the 3D memory device, allowing for in-memory computation and reducing the need for external data processing by integrating a data processing circuit on the same chip as the peripheral circuits, enabling high-speed data processing and improved I/O throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If peripheral circuits are formed outside the memory array in conventional 3D memory devices, then the memory array can be structured, but the array efficiency deteriorates and die size increases
Solution Approach 1:
The patent merges the peripheral circuits with the memory array by forming the peripheral circuits within the memory array structure itself. Specifically, select lines are extended through the entire memory array, and transistors are formed at intersections of word lines and bit lines within the array, eliminating the need for separate peripheral circuit regions and thereby improving array efficiency while maintaining compact die size.
2Productivity
If data processing is performed externally, then the memory device can operate, but the I/O interface burden increases and throughput is limited
Solution Approach 1:
The patent implements self-service by integrating data processing functionality directly within the memory device. The peripheral circuits formed within the memory array enable data processing operations to be performed locally without requiring extensive external processing, thereby reducing the I/O interface burden and increasing overall throughput.
3Ease of manufacture
If peripheral circuits are formed outside the memory array, then circuit functionality can be achieved, but resource utilization increases and cost rises
Solution Approach 1:
The patent combines peripheral circuit functionality with the memory array structure by forming select lines, word lines, and bit lines within the array. This merging approach reduces the total resource utilization by eliminating redundant structures and simplifies manufacturing by creating a more integrated device architecture.
Data Source
AI summary
Three-dimensional (3D) memory devices are provided. An exemplary 3D memory device includes a first semiconductor structure including a peripheral circuit, a data processing circuit, and a first bonding layer including a plurality of first bonding contacts. The peripheral circuit and the data processing circuit are stacked over one another vertically on different planes. The 3D memory device also includes a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts. In addition, the 3D memory device includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.