3D Memory Conductive Layer Structure for Thin Low-Current Stacks
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Solution Overview
Problem
Conventional methods face challenges in forming conductive layers for 3D memory devices with high element density and small size, particularly in reducing the thickness of conductive layers to below 10 nm, which complicates the manufacturing process and increases operational current.
Innovation Solution
The conductive layers are formed using a partial replacement process, where edge portions with lower resistance materials are added to center portions, reducing the overall resistance and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of conductive layers is reduced to below 10 nm to increase element density, then the storage capacity per unit volume increases, but the manufacturing process becomes more complex and operational current increases
Solution Approach 1:
The conductive layer is segmented into two distinct regions: a center portion and edge portions. The center portion uses a first conductive material while the edge portions use a second conductive material with lower resistance. This segmentation allows each region to be optimized independently, simplifying the overall manufacturing process while maintaining thin layer thickness for high density.
Solution Approach 2:
Different regions of the conductive layer are assigned different material properties. The center portion uses a material optimized for certain electrical characteristics, while the edge portions use a material with lower resistance to reduce overall layer resistance. This local differentiation enables the thin conductive layer to function effectively without increasing manufacturing complexity.
2Quantity of substance
If the thickness of conductive layers is reduced to below 10 nm to increase element density, then the storage capacity per unit volume increases, but the operational current increases
Solution Approach 1:
The edge portions of the conductive layer are assigned a second conductive material specifically selected for its lower resistance property. This local quality enhancement at the edges compensates for the increased resistance that would normally result from reducing the overall layer thickness, thereby reducing operational current while maintaining high element density.
Solution Approach 2:
The conductive layer is formed as a composite structure combining two different conductive materials. The first conductive material in the center portion and the second conductive material in the edge portions work together to achieve both thin thickness (for high density) and low overall resistance (for low operational current).
Data Source
AI summary
A semiconductor device includes a stack and a plurality of vertical pillar structures disposed in the stack. The stack includes a plurality of insulating layers and a plurality of conductive layers alternately arranged, each of the conductive layers includes a center portion and a plurality of edge portions at edges of the center portion, wherein a resistance of a material of the edge portions is less than a resistance of a material of the center portion. Each of the vertical pillar structures includes a conductive core, a shell electrode on a sidewall of the conductive core, and an ovonic threshold switch (OTS) layer on a sidewall of the shell electrode. A method of forming the semiconductor device is also disclosed.