3D Memory Cell Layout With Reduced Conductor Congestion
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Solution Overview
Problem
The challenge of increasing the degree of integration in memory devices while managing the size and complexity of constituent elements, particularly the arrangement of conductors, is addressed in the context of three-dimensionally arrayed memory cells.
Innovation Solution
The memory device employs a configuration where only two contacts are arranged in the Y direction within the CP region, allowing for efficient arrangement of conductors and reducing the size of memory blocks by increasing the number of layers, while maintaining the number of contacts in the X direction, thereby optimizing conductor placement and reducing block size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of constituent elements is increased to increase the degree of integration, then the storage capacity is improved, but the block size becomes excessively large
Solution Approach 1:
The patent transitions from a two-dimensional arrangement of memory cells to a three-dimensional structure by introducing vertical stacking of multiple layers. Memory cells are arranged across multiple layers in the vertical direction, allowing increased storage capacity without proportionally increasing the planar block size. This dimensional change enables higher integration density while controlling the footprint area.
2Quantity of substance
If the dimensions are increased to accommodate more memory cells, then the degree of integration is improved, but the conductor arrangement becomes excessively complex
Solution Approach 1:
The patent divides the conductor system into multiple independent layers, with each layer containing a subset of conductors. This segmentation allows each layer to be designed and routed independently, reducing the complexity of conductor arrangement. Conductors in different layers can be optimized separately, making the overall system more manageable despite the increased number of memory cells.
Solution Approach 2:
The patent utilizes the vertical dimension to separate conductors into multiple stacked layers. By distributing conductors across different vertical levels, the patent reduces planar congestion and simplifies routing complexity. This three-dimensional conductor arrangement allows for more efficient wire placement and reduces interference between adjacent conductors.
Data Source
AI summary
A first semiconductor extends in a first direction. A first pillar extends in a second direction crossing the first direction and is in contact with the first semiconductor. A first conductor is coupled to an end of the first pillar on a side in the second direction and extends in a third direction crossing the first direction and the second direction. A first transistor is provided farther in the second direction than the first conductor and coupled to the first conductor. A second conductor is provided farther in the second direction than the first conductor, extends in the third direction, and is coupled to the first transistor.