3D Memory Stack Contact Formation with Simultaneous Gate Deposition
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Solution Overview
Problem
The manufacturing process of 3D NAND memory devices is complex and costly, limiting the memory density and performance of planar memory cells, which are scaled to smaller sizes using 2D processes that approach an upper limit.
Innovation Solution
A method for forming a 3D semiconductor device involving the formation of a stack structure with alternating sacrificial and dielectric layers, gate line slits, contact vias, and conductive layers, where sacrificial layers are replaced with conductive materials through etching and deposition processes, simplifying the manufacturing process and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional separate formation processes for conductive layers and contacts are used, then manufacturing precision is maintained, but device complexity and manufacturing time increase
Solution Approach 1:
The patent combines the formation of conductive layers and contacts into a single deposition process. The conductive material is deposited to form both the conductive layers replacing sacrificial layers and the contacts extending to the surface simultaneously, reducing the number of process steps while maintaining precision through controlled deposition parameters and sequence
Solution Approach 2:
The patent performs preliminary actions by first forming cavities and contact vias with precise geometries before depositing conductive material. The cavities are formed with specific depths and orientations, and contact vias are pre-positioned to ensure proper alignment and connection, enabling the subsequent combined deposition to achieve both conductive layers and contacts in one step
2Quantity of substance
If planar memory cell scaling is continued, then memory density increases, but manufacturing cost and process difficulty increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell scaling to three-dimensional vertical stacking. Multiple memory cells are arranged in vertical stacks with alternating conductive and dielectric layers, enabling increased memory density without requiring further reduction of lateral feature sizes, thus avoiding the manufacturing challenges associated with extreme scaling
Solution Approach 2:
The patent segments the memory structure into repeating units of alternating conductive layers and dielectric layers stacked vertically. Each stack contains multiple memory cells formed by combining channel structures with gate lines extending through the stacks, allowing modular fabrication and increased density through vertical multiplication rather than lateral division
3Reliability
If contact footprint is increased, then connection reliability improves, but device area increases
Solution Approach 1:
The patent extends contacts vertically from the substrate surface through the stacked structure to reach conductive layers at different heights. This vertical extension increases the effective contact footprint and connection area without requiring larger lateral device area, as the additional contact surface is achieved in the vertical dimension rather than by spreading out laterally
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the manufacturing process of 3D NAND memory devices, improves performance by enabling simultaneous formation of conductive layers and contacts, and increases memory density by allowing for a larger footprint of contacts, thereby enhancing the connection structure and device performance.
Implementation Method 1
forming conductive layers in replace of the sacrificial layers in the cavities and a contact in the contact via by depositing a conductive material in the contact via and the cavities
Implementation Method 2
removing part of the sacrificial layers in the second region to form a first cavity coupled to the contact via; and removing the sacrificial layers in the first region to form a second cavity
Data Source
AI summary
Methods, devices, and systems for three-dimensional (3D) memory devices are provided. In one aspect, a method for forming a three-dimensional (3D) semiconductor device includes: forming a first stack structure including a plurality of alternating sacrificial layers and dielectric layers, the first stack structure having a first region and a second region; forming gate line slits extending through the first stack structure in the first region and the second region; forming a contact via extending to a target sacrificial layer in the second region; forming cavities coupled to the contact via through the gate line slits; and forming conductive layers in replace of the sacrificial layers in the cavities and a contact in the contact via by depositing a conductive material in the contact via and the cavities. The 3D semiconductor device includes a second stack structure having the conductive layers and the dielectric layers.