3D Nonvolatile Memory Contact Structure for Penetration Depth Control
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in achieving high integration, reliability, and performance due to limitations in contact formation, particularly in three-dimensional structures where controlling the penetration depth of high-aspect-ratio contacts is difficult, leading to potential defects.
Innovation Solution
The proposed solution involves forming a nonvolatile memory device with a peripheral circuit region that includes a lower contact connected to the peripheral circuit element through a first interlayer insulating film, where the height of the top surface of the lower contact is lower than or equal to the height of the bottom surface of the lowermost gate pattern, and an upper contact connected to the lower contact through a second interlayer insulating film, allowing for improved control of contact penetration depth and reduced defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-aspect-ratio contacts are formed in three-dimensional memory structures, then integration degree is improved, but penetration depth control becomes difficult leading to defects
Solution Approach 1:
The contact structure is segmented into multiple parts: a lower contact extending through the first interlayer insulating film to a first depth, and an upper contact extending through a second interlayer insulating film to a second depth. This segmentation allows independent control of penetration depths for different contact portions, resolving the difficulty of controlling penetration depth in high-aspect-ratio contacts while maintaining high integration degree through three-dimensional stacked structure.
2Reliability
If contact penetration depth is increased to reach peripheral circuit elements, then connectivity is improved, but defect risk increases due to difficult depth control
Solution Approach 1:
The lower contact is formed in advance through the first interlayer insulating film to connect with the peripheral circuit element before forming the upper contact through the second interlayer insulating film. This preliminary action ensures proper connectivity is established early in the fabrication process, while the subsequent formation of the upper contact allows for controlled penetration depth without risking defects in the already-formed lower contact connection.
Data Source
AI summary
A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.