3D Memory Electrode Contacts With Differentiated Side Insulation

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Solution Overview

Problem

Existing semiconductor devices face challenges in enhancing data storage capacity while maintaining reliability and productivity, particularly in three-dimensionally arranged memory cells.

Innovation Solution

The semiconductor device incorporates a memory cell structure with a unique electrode stacking structure and electrode contact portions, featuring distinct side insulation layers to facilitate stable through-hole formation and simplify the gate contact formation process, thereby reducing the connection area and enhancing reliability and productivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If three-dimensionally arranged memory cells are used to increase data storage capacity, then storage capacity is improved, but manufacturing complexity and reliability challenges increase

Engineering Contradiction:
Improvedata storage capacityVSAvoidmanufacturing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The electrode stacking structure is divided into multiple electrodes (first electrode, second electrode, third electrode) with distinct side insulation layers, allowing independent formation and control of each electrode-contact portion interface. This segmentation enables precise manufacturing of complex 3D structures while maintaining reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different side insulation layers are applied to different electrodes based on their specific requirements. The first side insulation layer is between the first electrode and first contact portion, the second side insulation layer is between the second electrode and second contact portion, and the third side insulation layer is between the third electrode and third contact portion. This local differentiation allows optimized manufacturing for each region.

Inventive Principle:
Principle #3Local quality

2Reliability

If conventional electrode contact formation is used in 3D stacking structure, then connection is achieved, but connection area is large and reliability is reduced

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidconnection area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from planar 2D contact formation to vertical 3D contact formation by stacking multiple electrodes and contact portions in the thickness direction. This dimensional change reduces the lateral connection area while maintaining electrical connectivity through the vertical dimension, thereby improving reliability without sacrificing connection functionality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If through-holes are formed in electrode stacking structure, then electrical connection is achieved, but formation process is complex and productivity is reduced

Engineering Contradiction:
Improvemanufacturing productivityVSAvoidthrough-hole formation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Side insulation layers are formed on the electrodes before forming the contact portions. This preliminary action simplifies the subsequent through-hole formation process by providing pre-defined boundaries and protection, reducing the complexity of the overall manufacturing process while maintaining productivity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The side insulation layers act as intermediary elements between the electrodes and contact portions. These intermediary layers facilitate the formation process by providing a controlled interface, simplifying the through-hole formation process and improving manufacturing productivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4700825A1Semiconductor device and electronic system including the same
Publication Date: 2026.02.25 SAMSUNG ELECTRONICS CO LTD
  • EP4700825A1 patent drawingFigure 1
  • EP4700825A1 patent drawingFigure 2
  • EP4700825A1 patent drawingFigure 3

AI summary

A semiconductor device includes a memory cell structure in a cell array region (102), an electrode stacking structure (120) including a plurality of electrodes (130) and a plurality of interlayer insulation layers alternately stacked in a connection region, and a plurality of electrode contact portions (190) penetrating at least a partial portion of the electrode stacking structure (120) and are electrically connected to the plurality of electrodes (130). The plurality of electrode contact portions (190) include first and second contact portions (196). The first contact portion (192) includes a first conductive portion (192c), and a first side insulation layer (192i) between the electrode stacking structure (120) and the first conductive portion (192c). The second contact portion (196) includes a second conductive portion (196c), and a second side insulation layer (196i) between the electrode stacking structure (120) and the second conductive portion (196c). The second side insulation layer (196i) has a shape or a structure different from a shape or a structure of the first side insulation layer (192i).