3D Non-Volatile Memory Cell Contact Layout for Higher Integration
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Solution Overview
Problem
The challenge of increasing the degree of integration in non-volatile memory devices while maintaining performance and reducing costs is hindered by the need for ultra-high-priced equipment to form fine patterns, which limits the integration of two-dimensional devices, and three-dimensional arrangements are proposed to address this.
Innovation Solution
A non-volatile memory device design featuring a substrate with a cell array region and extension region, including stacked gate electrodes and mold insulating layers, a channel structure intersecting the electrodes, a cell contact electrically connected to a selection gate, an insulating ring between non-selection gate electrodes, and a high dielectric constant layer with specific overlapping and non-overlapping portions, enhancing integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar non-volatile memory device structure is used, then manufacturing process is simpler, but degree of integration is limited
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional structure by stacking multiple gate electrodes (first gate electrode, second gate electrode, third gate electrode) vertically over the channel structure. This vertical stacking enables higher degree of integration by utilizing the third dimension (height) rather than only expanding in the plane, thereby increasing the quantity of memory elements without requiring ultra-high-priced fine pattern equipment.
2Quantity of substance
If three-dimensional non-volatile memory device structure is used, then degree of integration is increased, but device complexity increases
Solution Approach 1:
The patent segments the gate structure into multiple distinct gate electrodes (first gate electrode connected to first gate line, second gate electrode connected to second gate line, third gate electrode connected to third gate line), each independently controllable through separate gate lines. This segmentation allows complex three-dimensional functionality to be managed through modular, independently addressable components, reducing the effective complexity despite the increased integration density.
Solution Approach 2:
The stacked gate electrodes serve multiple functions: the first gate electrode controls the first memory cell, the second gate electrode controls the second memory cell, and the third gate electrode controls the third memory cell. Each gate electrode can be independently activated to select specific memory cells for read, write, or erase operations, enabling multi-functional control from a single vertical stack structure.
3Quantity of substance
If fine pattern formation is used to increase integration, then degree of integration is improved, but manufacturing cost increases
Solution Approach 1:
Instead of achieving higher integration through finer lateral patterning (which requires expensive equipment), the patent achieves increased integration through vertical stacking of gate electrodes. This approach utilizes the height dimension to pack more memory cells within the same footprint, avoiding the need for ultra-high-priced fine pattern formation equipment while maintaining or improving integration density.
Data Source
AI summary
A non-volatile memory device comprises a substrate, a mold structure that includes gate electrodes stacked on the substrate and mold insulating layers alternately stacked with the gate electrodes, a cell contact on the substrate, wherein the cell contact is electrically connected to a selection gate electrode of the gate electrodes and is not electrically connected to a non-selection gate electrode of the gate electrodes, an insulating ring on the substrate, wherein the insulating ring is between the non-selection gate electrode and a sidewall of the cell contact and is in contact with the non-selection gate electrode, and a high dielectric constant layer between respective ones of the gate electrodes and the mold insulating layers, wherein the insulating ring includes a first portion that overlaps the high dielectric constant layer in a vertical direction, and a second portion that does not overlap the high dielectric constant layer in the vertical direction.