3D Memory Contact Plug Structure for Reliable Vertical Connectivity

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Solution Overview

Problem

Existing semiconductor devices face challenges in increasing data storage capacity while maintaining reliability and mass productivity.

Innovation Solution

A semiconductor device with a three-dimensional arrangement of memory cells, featuring a substrate with circuit devices and lower interconnection lines, and a second semiconductor structure with stacked gate electrodes, channel structures, contact plugs, and support structures, each with specific width variations and conductive layers, including voids to enhance connectivity and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but device complexity increases

Engineering Contradiction:
Improvedata storage capacityVSAvoiddevice complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent implements three-dimensional memory cell arrangement by stacking gate electrodes vertically over channel structures, transitioning from two-dimensional to three-dimensional spatial utilization. This enables increased storage capacity by exploiting the vertical dimension while maintaining manufacturability through standardized stacking processes

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The memory device is segmented into distinct functional regions: channel structures penetrating gate electrodes in the first region, and contact plugs penetrating gate electrodes in the second region. This segmentation allows independent optimization of storage and connectivity functions, managing overall device complexity

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If contact plugs have uniform width throughout their length, then manufacturing is simpler, but connectivity reliability deteriorates due to stress concentration

Engineering Contradiction:
Improveease of manufactureVSAvoidconnectivity reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The contact plug is designed with asymmetric width distribution: wider at the upper portion and narrower at the lower portion. This asymmetric geometry reduces stress concentration at the narrow lower section while maintaining adequate connectivity area at the upper section, improving reliability without significantly complicating manufacturing

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

Different sections of the contact plug have different widths tailored to their specific functional requirements. The upper wider portion handles electrical connectivity, while the lower narrower portion provides structural support and stress distribution, optimizing both reliability and manufacturability

Inventive Principle:
Principle #3Local quality

3Reliability

If conductive layers are made thinner to reduce resistance, then electrical conductivity is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveelectrical conductivityVSAvoidmanufacturing precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The contact plug employs a composite structure with multiple conductive layers of different materials and thicknesses. This composite approach allows optimization of electrical conductivity through material selection while managing manufacturing precision requirements through the layered architecture, where each layer can be independently controlled

Inventive Principle:
Principle #40Composite materials

4Quantity of substance

If gate electrodes are stacked vertically to increase storage capacity, then data storage capacity is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvedata storage capacityVSAvoidmanufacturing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

Gate electrodes are stacked vertically in the first direction perpendicular to the substrate, utilizing the vertical dimension to increase storage capacity. This three-dimensional arrangement maintains manufacturing feasibility by using standard deposition and patterning processes extended to multiple layers

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12588496B2Semiconductor device and data storage system including the same
Publication Date: 2026.03.24 SAMSUNG ELECTRONICS CO LTD
  • US12588496B2 patent drawing
  • US12588496B2 patent drawing
  • US12588496B2 patent drawing

AI summary

A semiconductor device includes a substrate; a conductive layer; and a contact plug connected to the conductive layer. The contact plug includes a first portion; and a second portion, sequentially stacked, wherein a width of an upper surface of the first portion is wider than a width of a lower surface of the second portion. The contact plug includes a barrier layer; a first conductive layer on the barrier layer; and a second conductive layer on the first conductive layer. The second conductive layer comprises voids. The barrier layer, the first conductive layer, and the second conductive layer extend continuously in the first and second portions. The barrier layer has a first thickness, the second conductive layer has a second thickness, equal to or greater than the first thickness, and the first conductive layer has a third thickness, equal to or greater than the second thickness.