3D Memory Channel Hole Structure for Lower Contact Resistance
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high data storage capacity and reliable operating characteristics, particularly in three-dimensional memory cell arrangements.
Innovation Solution
The semiconductor device incorporates a first substrate structure with circuit elements, bonding layers, and a second substrate structure featuring a plate layer, intermediate insulating layer, gate electrodes, interlayer insulating layers, a channel structure with dielectric and semiconductor layers, and bonding layers, where the channel hole dimensions and layer configurations enhance contact area and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but contact resistance and operating reliability deteriorate
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by stacking multiple substrate structures vertically. The channel structure extends in the first direction (vertical) through multiple layers including intermediate insulating layers and stack structures, enabling high-density storage while maintaining reliable electrical contact through optimized vertical conduction paths.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the three-dimensional memory device. The channel structure has specific dielectric and semiconductor layers with tailored properties, the intermediate insulating layer has distinct characteristics from the stack structure, and bonding layers are strategically positioned to optimize local electrical contact and reduce contact resistance in critical regions.
2Quantity of substance
If three-dimensional memory structure is implemented to increase storage capacity, then storage density is improved, but contact area is reduced leading to increased contact resistance
Solution Approach 1:
The channel structure is nested within the channel hole that passes through the intermediate insulating layer and stack structure. The dielectric layer and semiconductor layers are nested concentrically within the channel hole, creating a multi-layer nested configuration that maximizes contact area while maintaining compact three-dimensional storage density.
Solution Approach 2:
The channel structure comprises composite materials including dielectric layer, first semiconductor layer, second semiconductor layer, and buried layer with different electrical and physical properties. This composite structure optimizes both contact area for reduced resistance and storage density by utilizing materials with complementary characteristics in different regions of the channel structure.
Data Source
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AI summary
A semiconductor device may include a first substrate structure (S1) including a substrate, circuit elements on the substrate, and first bonding layers on the circuit elements, and a second substrate structure (S2) on the first substrate structure. The second substrate structure may include a plate layer (101), an intermediate insulating layer (102) below the plate layer and including silicon nitride, gate electrodes (130L, 130M) below the intermediate insulating layer and stacked to be spaced apart from each other in a vertical direction (Z), a channel structure (CH) in a channel hole passing through the intermediate insulating layer and the gate electrodes and including a semiconductor layer (141, 142), and second bonding layers connected to the first bonding layers. The channel hole may have a first width in a first portion passing through the gate electrodes and a second width, wider than the first width, in a second portion passing through the intermediate insulating layer.