3D Memory Multi-Stack Contacts for Low-Resistance BL-SL Connection
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Solution Overview
Problem
Current memory devices face challenges in achieving high-density storage without performance degradation, particularly in multiple-stack deposition processes, where lithography misalignment affects contact resistance between bit lines (BL) and source/select lines (SL), impacting read current and speed.
Innovation Solution
A three-dimensional (3D) memory system is developed with ferroelectric memory cells, featuring enlarged nail-like drain/source structures and improved contact resistance between BL and SL, allowing for multiple-stack processing without performance degradation, even with lithography misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-density storage is achieved through multi-stack 3D memory structure, then storage capacity increases, but contact resistance between bit lines and source/select lines increases due to lithography misalignment
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional multi-stack architecture, stacking multiple memory device layers vertically. This dimensional change enables high-density storage by utilizing the vertical space dimension, accommodating more memory cells per chip area while maintaining electrical connectivity through carefully designed contact structures that penetrate through multiple layers.
Solution Approach 2:
The patent implements nested contact structures where bit line contact structures are positioned within and connected to source/select line contact structures across multiple stacked layers. The contact structures are nested vertically through the stack, with lower-layer contacts connected to upper-layer contacts, creating a hierarchical nested configuration that maintains low contact resistance despite the multi-stack complexity.
2Quantity of substance
If multiple-stack ferroelectric memory cells are used to increase density, then storage capacity improves, but read speed degrades due to increased contact resistance
Solution Approach 1:
The patent employs preliminary action by pre-forming contact structures with extended lateral dimensions before final patterning. The contact structures are initially formed larger than the final required size, allowing subsequent lithography steps to trim them to precise final dimensions. This preliminary oversized formation ensures that even if lithography misalignment occurs during subsequent steps, the contact structures maintain adequate overlap and connection area, preserving low contact resistance and fast read speeds in the final multi-stack device.
3Ease of manufacture
If conventional lithography alignment is used in multi-stack fabrication, then manufacturing process remains simple, but lithography misalignment causes performance degradation
Solution Approach 1:
The patent applies preliminary action by forming contact structures with intentionally oversized lateral dimensions before subsequent lithography patterning steps. This preliminary oversized formation creates a tolerance buffer that accommodates potential lithography misalignment in later fabrication steps. The contact structures are trimmed to final dimensions after alignment-critical steps are completed, ensuring that even with conventional lithography alignment, the final device achieves the required manufacturing precision without performance degradation.
Solution Approach 2:
The patent implements beforehand cushioning by designing contact structures with extended lateral dimensions that provide a built-in tolerance buffer against lithography misalignment. This cushioning design ensures that even if alignment errors occur during subsequent fabrication steps, the contact structures maintain sufficient overlap and electrical connection area, preventing performance degradation and protecting the device against manufacturing variations.
Data Source
AI summary
A memory device includes a first memory array including: a plurality of memory strings spaced from each other along a first lateral direction and a second lateral direction, each of the plurality of memory strings including a plurality of memory cells arranged along a vertical direction; and a plurality of first conductive structures extending along the vertical direction; wherein each of the plurality of first conductive structures includes a first portion and a second portion; wherein the first portion extends across the plurality of memory cells of a corresponding pair of the plurality of memory strings along the vertical direction, and the second portion is disposed over the first portion along the vertical direction; and wherein the second portion extends farther than the first portion along at least one of the first or second lateral direction.