3D Memory Contact Staircase Layout for Dense Array Integration
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Solution Overview
Problem
As feature sizes of planar memory cells approach a lower limit, planar processes and fabrication techniques become challenging and costly, leading to a density limitation in planar memory cells.
Innovation Solution
A three-dimensional (3D) memory device is formed with first and second memory arrays on a semiconductor layer, a staircase structure between them, and contact regions with through-silicon contacts (TSCs) extending through an insulating layer into the semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then storage density is improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture. The memory structures are formed vertically extending from the substrate, utilizing the third dimension (height) to increase storage density without further reducing feature sizes. This dimensional change allows continued density improvement while avoiding the manufacturing complexity associated with scaling planar cells to smaller sizes.
2Quantity of substance
If feature sizes of planar memory cells are reduced, then storage density is improved, but fabrication cost increases
Solution Approach 1:
By moving to 3D vertical memory structures, the patent achieves higher storage density without requiring further reduction of lateral feature sizes. This approach avoids the exponentially increasing fabrication costs associated with sub-10nm planar scaling, as the manufacturing processes can operate at more economical feature sizes while gaining density through vertical stacking.
Solution Approach 2:
The 3D memory structure is divided into multiple discrete components including alternating layers of first and second materials, with memory holes formed through selective removal. This segmentation allows each layer and component to be manufactured using standard processes at larger, more cost-effective feature sizes, rather than requiring entire structures to be scaled down.
3Quantity of substance
If three-dimensional memory architecture is implemented, then storage density is improved, but contact structure formation complexity increases
Solution Approach 1:
The patent performs preliminary actions during the alternating layer formation process by creating sacrificial regions and defining memory hole locations before final structure completion. Contact holes are formed through the alternating layers at predetermined locations, and conductive materials are deposited in advance to establish electrical connections before the memory structures are fully assembled, simplifying subsequent fabrication steps.
Solution Approach 2:
The patent uses alternating layers of first and second materials as intermediary structures that facilitate both memory formation and contact creation. These alternating layers serve as both the memory storage medium and the structural framework through which contact holes are formed and conductive interconnects are established, reducing the complexity of separate contact formation processes.
Data Source
AI summary
The present disclosure describes a three-dimensional (3D) memory device includes first and second memory arrays disposed on a semiconductor layer. The 3D memory device can also include a staircase structure disposed between the first and second memory arrays. The staircase structure includes first and second staircase regions. The first staircase region includes a first staircase structure that contains a first plurality of stairs descending in a first direction. The second staircase region includes a second staircase structure that contains a second plurality of stairs descending in a second direction. The 3D memory device can also include a contact region disposed between the first and second staircase regions. The contact region includes a plurality of contacts the extending through an insulating layer and into the semiconductor layer.