3D Memory Contact Structure for Stress Leakage Mitigation
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Solution Overview
Problem
Planar memory cells face density limitations and fabrication challenges as feature sizes approach a lower limit, making 3D memory architectures necessary to enhance memory density.
Innovation Solution
A 3D memory device with a stack structure comprising interleaved dielectric and conductive layers, featuring a contact structure with an interconnect member that connects to a conductive layer, where the interconnect member's thickness is greater than the conductive layer's thickness, and includes liner layers to address signal communication issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but fabrication becomes challenging and costly when feature sizes approach a lower limit
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture. The memory device includes a stack structure with multiple alternating dielectric layers and conductive layers stacked vertically, enabling memory density improvement by utilizing the vertical dimension rather than continuing to scale lateral feature sizes.
2Reliability
If the interconnect member has the same thickness as the conductive layer, then manufacturing is simpler, but stress leakage occurs and signal communication is degraded
Solution Approach 1:
The interconnect member is designed with non-uniform thickness, being thicker at the ends connected to contact structures and thinner in the middle section. This local variation in thickness optimizes stress distribution and signal communication at critical interfaces while maintaining overall structural integrity, addressing specific local requirements rather than applying a uniform thickness throughout.
Solution Approach 2:
The patent changes the thickness parameter of the interconnect member from a uniform value to a variable value along its length. The interconnect member thickness is specifically designed to be greater than the conductive layer thickness at the connection interfaces, creating a step structure that mitigates stress leakage and improves signal communication.
3Reliability
If the connection interface is positioned at the same level as the conductive layer, then manufacturing alignment is easier, but stress leakage and signal communication issues arise
Solution Approach 1:
The interconnect member is designed with extended thickness before the actual connection is made, creating a preparatory structure that protrudes beyond the conductive layer level. This preliminary extension allows for better stress distribution and signal coupling at the interface, with the thicker portion serving as a stress-relief zone before the connection point.
Data Source
AI summary
In certain aspects, a memory device is provided. The memory device includes a stack structure and a contact structure. The stack structure includes a first stack structure including interleaved first dielectric layers and second dielectric layers, and a second stack structure including interleaved first dielectric layers and conductive layers. The contact structure includes a contact member extending, in a first direction, through the first stack structure and includes an interconnect member extending in a second direction perpendicular to the first direction to connect with a first conductive layer extended from the second stack structure. The interconnect member is arranged at an end of the contact member and connected with the contact member. In the first direction, a thickness of the interconnect member is greater than a thickness of the first conductive layer extended from the second stack structure.