3D Memory Contact Structures Without Staircase Footprint Growth
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Solution Overview
Problem
The challenge in 3D NAND memory devices is the reduction in effective storage capacity per area due to the increased lateral dimensions of the staircase structure, which also introduces mechanical stress and reliability issues.
Innovation Solution
A three-dimensional (3D) memory structure that eliminates the need for a staircase structure by using coplanar contact structures electrically connected to a substrate, with isolation liners to prevent electrical interference, and includes dummy memory strings for structural support and process variation control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of vertically stacked memory cells is increased to increase storage density, then the storage capacity is improved, but the lateral dimensions of the staircase structure are increased, which reduces the effective storage capacity per area
Solution Approach 1:
The patent transitions from a planar staircase structure to a three-dimensional contact structure where contacts are formed at multiple depths within the memory stack. This allows electrical connections to be made without extending the lateral footprint, effectively utilizing the vertical dimension to maintain high storage density while providing necessary electrical access points.
Solution Approach 2:
The contact structures are nested within the memory stack itself, with conductive contacts formed at various levels within the alternating conductive and dielectric layers. This nesting approach allows multiple contact points to be integrated within the existing stack volume without requiring additional lateral space.
2Reliability
If the lateral dimensions of the staircase structure are increased to provide electrical contacts, then the electrical connectivity is improved, but mechanical stress between the memory array region and the staircase region is increased, causing reliability problems
Solution Approach 1:
The patent extracts the staircase structure entirely from the design, removing the source of mechanical stress. Instead, isolated contact structures are formed directly within the memory stack, eliminating the large lateral interface between the memory array and staircase region that caused stress-related reliability issues.
3Reliability
If the staircase structure is used to provide electrical contacts, then the electrical connectivity between word lines and control gates is achieved, but the effective storage capacity per area is reduced
Solution Approach 1:
The patent utilizes the vertical dimension by forming contacts at multiple depths within the stack rather than requiring lateral extension. This allows electrical connectivity to be achieved while maintaining a compact lateral footprint, thereby preserving effective storage capacity per area.
Data Source
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AI summary
Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.