3D Memory Contact Structure Layout for Single-Loop VIA Formation
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in forming contact structures of different sizes along a vertical direction without causing tungsten loss and increasing manufacturing costs, particularly in forming longer and shorter contact structures using multiple etching masks and processes.
Innovation Solution
The technique involves forming contact structures and vertical interconnect access (VIA) contacts in a single manufacturing loop before bonding the first semiconductor structure to the second, allowing for the combination of bottom top metal and VIA into a single conductive structure made of aluminum, reducing manufacturing costs and increasing production yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple etching masks and processes are used to form contact structures of different sizes, then manufacturing precision is improved, but manufacturing cost increases and production yield decreases
Solution Approach 1:
The patent combines the formation of bottom top metal and VIA contacts into a single manufacturing loop, forming both contact structures of different sizes simultaneously without requiring separate etching masks and processes. This merging approach maintains manufacturing precision while eliminating the productivity losses and cost increases associated with multiple sequential processes.
2Manufacturing precision
If multiple etching masks and processes are used to form contact structures of different sizes, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges the formation of bottom top metal and VIA contacts into a single manufacturing loop, eliminating the need for multiple etching masks and processes. This reduces manufacturing complexity and cost while maintaining the precision required for forming contact structures of different sizes through a unified process approach.
3Productivity
If contact structures are formed in a single manufacturing loop, then productivity is improved, but manufacturing precision may deteriorate
Solution Approach 1:
The patent successfully merges bottom top metal and VIA contact formation into a single manufacturing loop while maintaining manufacturing precision. This is achieved through a unified process that forms both contact structures of different sizes simultaneously, improving productivity and production yield without sacrificing the dimensional accuracy required for proper device function.
Data Source
AI summary
The present disclosure relates to methods, devices, systems, and techniques for manufacturing contact structures in semiconductor devices, e.g., 3D memory devices such as DRAM. An example semiconductor device includes a first semiconductor structure and a second semiconductor structure connected together. The first semiconductor structure includes a first contact structure extending along a first direction and an array of memory cells. The first contact structure includes a first cross section and a second cross section both perpendicular to the first direction. The first cross section is farther away from the second semiconductor structure than the second cross section along the first direction. A size of the first cross section is smaller than a size of the second cross section.