3D Memory Contact Via Structure Reducing Chip Area
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in reducing chip size and manufacturing cost due to the need for increased word lines, contact area, and deeper via cavities, which complicate interconnection and increase processing complexity.
Innovation Solution
A combined support pillar/word line contact via structure/peripheral region interconnection via structure that provides structural support and electrical contact, reducing chip area and cost by simplifying the interconnection process between word lines and peripheral devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If increased word lines and deeper via cavities are used to achieve ultra-high density storage, then storage capacity is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the support pillar structure with the word line contact via structure into a single integrated feature. The support pillar serves dual purposes: providing mechanical support to the alternating stack and serving as the contact via to connect word lines to peripheral devices. This merging eliminates the need for separate support pillars and reduces via cavity depth requirements, thereby reducing device complexity while maintaining storage capacity.
Solution Approach 2:
The support pillar/word line contact via structure performs multiple functions simultaneously: (1) provides structural support to the alternating stack of insulating and spacer material layers, (2) serves as the contact via for electrical connection between word lines and peripheral devices, and (3) enables interconnection in peripheral regions. This multi-functionality reduces the number of separate structures needed, simplifying the overall device architecture.
2Reliability
If increased contact area is provided for word line connections, then electrical connection reliability is improved, but chip area increases
Solution Approach 1:
The patent transitions from a traditional planar contact approach to a vertical three-dimensional contact structure. The support pillar/word line contact via extends vertically through the alternating stack, providing electrical connection in the vertical dimension rather than requiring expanded horizontal contact area. This dimensional change allows reliable electrical connection while maintaining compact chip footprint.
Solution Approach 2:
The word line contact via structure is nested within the support pillar structure. The contact via is formed within the same vertical footprint as the support pillar, utilizing the same lateral space for dual purposes. This nesting arrangement provides reliable electrical connection without increasing chip area, as the contact function is embedded within the existing support structure.
Data Source
AI summary
A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-insulated structure includes a conductive via structure having an upper conductive via portion overlying and contacting an annular area of a top surface of one of the electrically conductive layers, a lower conductive via portion having a lesser lateral dimension than the upper conductive via portion and extending through at least a bottommost one of the electrically conductive layers, and an interconnection conductive via portion located between the upper conductive via portion and the lower conductive via portion and contacting a cylindrical sidewall of the one of the electrically conductive layers.