3D Memory Staircase Layout for High-Density Contact Vias
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Solution Overview
Problem
Existing three-dimensional memory devices face challenges in increasing contact via density and optimizing the structure for efficient electrical connectivity between memory arrays.
Innovation Solution
The proposed solution involves forming a three-dimensional memory device with a staircase configuration that includes an alternating stack of insulating and conductive layers, featuring stepped cavities and bridge regions with variable widths, and employing a method that involves multiple iterations of lithographic patterning and anisotropic etching to create asymmetric contact via structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional planar structure is used for memory arrays, then the manufacturing process is simpler, but the contact via density is lower
Solution Approach 1:
The patent transitions from a conventional planar (2D) memory array structure to a three-dimensional staircase structure. The staircase configuration introduces vertical dimensionality with multiple terraces and stepped surfaces, allowing contact vias to be formed at multiple elevation levels. This dimensional transformation enables significantly higher contact via density within the same footprint area, as vias can be distributed across different vertical planes rather than being confined to a single plane.
Solution Approach 2:
The memory array is segmented into multiple discrete terraces or steps at different elevation levels. Each terrace can independently accommodate contact vias, and the segmentation allows for optimized via placement on each level. The alternating conductive and insulating layers are also segmented into distinct horizontal strata, creating a layered architecture that facilitates high-density via formation while maintaining manufacturing feasibility through modular processing.
2Area of stationary object
If the inter-array region is minimized to increase array density, then the device area is reduced, but the electrical connectivity between arrays deteriorates
Solution Approach 1:
The patent utilizes the vertical dimension to maintain electrical connectivity between memory arrays while minimizing the horizontal inter-array spacing. Conductive bridge regions extend through the vertical stack, connecting arrays at multiple elevation levels. This allows the horizontal distance between arrays to be reduced while compensating for the shorter lateral connection paths with multiple vertical connection points, thereby maintaining overall connectivity reliability.
Solution Approach 2:
The patent merges multiple conductive pathways at different vertical levels into a unified inter-array connection system. The alternating conductive layers form continuous or discontinuous bridge regions that span the inter-array region, creating redundant parallel paths for electrical current. This merging of multiple connection layers provides both area efficiency and connectivity reliability, as failure in one path can be compensated by other paths.
3Reliability
If symmetric contact via structures are used, then the manufacturing process is simpler, but the electrical connectivity efficiency is lower
Solution Approach 1:
The patent employs asymmetric contact via structures where vias on different terraces have different geometries, positions, or connection configurations. For example, vias on upper terraces may connect to different conductive layers or have different lateral offsets compared to vias on lower terraces. This asymmetry optimizes electrical connectivity by creating direct, short-current paths tailored to each via's specific location and function, while the manufacturing complexity is managed through systematic patterning processes that can accommodate the asymmetric designs.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a first three-dimensional memory array located in a first memory array region, and a second three-dimensional memory array located in a second memory array region that is laterally spaced from the first memory array region along a first horizontal direction by an inter-array region. The alternating stack is laterally bounded by two trench fill structures that are laterally spaced apart along a second horizontal direction by an inter-trench spacing. The inter-array region includes a stepped cavity having vertical steps of the alternating stack that laterally extend along different horizontal directions. Multiple rows of contact via structures may contact different electrically conductive layers in the stepped cavity. Alternatively or additionally, a top portion of the stepped cavity and a width of a bridge region of the electrically conductive layers in the inter-array region may have a variable lateral extent along the second horizontal direction.