3D Memory Word Line Contact Wells With Stepped Void-Tolerant Structure

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Solution Overview

Problem

Current three-dimensional memory devices face challenges in efficiently forming multi-level word line contact wells, which affect the structural integrity and performance of memory devices due to mechanical stress and void tolerance issues in the dielectric fill structures.

Innovation Solution

The formation of contact wells with stepped bottom edges and vertically-extending edge segments, filled with dielectric materials and contact via structures that contact electrically conductive layers, allows for reduced mechanical stress and tolerance of voids, improving the structural integrity and performance of memory devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional contact well structures are used, then manufacturing process is simpler, but mechanical stress increases and void tolerance decreases

Engineering Contradiction:
Improvestructural integrityVSAvoidcontact well structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The contact well structure is segmented into multiple levels with stepped bottom edges, where each level corresponds to different electrically conductive layers. This segmentation allows the structure to accommodate multiple word lines at different heights, reducing mechanical stress by distributing loads across multiple levels rather than concentrating them at a single bottom surface.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The contact well structure transitions from a conventional single-level bottom surface to a multi-level stepped structure with vertically-extending edge segments. This dimensional change in the vertical direction allows the contact well to interface with multiple electrically conductive layers at different heights, improving void tolerance and mechanical stress distribution.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If stepped bottom edge contact wells are formed, then void tolerance improves, but manufacturing precision requirements increase

Engineering Contradiction:
Improvevoid toleranceVSAvoidstepped bottom edge formation
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The stepped bottom edges are formed preliminarily during the contact well formation process itself, rather than requiring subsequent complex machining or etching steps. The vertically-extending edge segments are created as integral parts of the contact well structure, allowing voids to be naturally accommodated without requiring high-precision post-processing.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If multiple electrically conductive layers are contacted, then device functionality improves, but contact well complexity increases

Engineering Contradiction:
Improvemulti-level word line contactVSAvoidcontact well structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The contact well structure serves multiple functions simultaneously: it provides mechanical support, accommodates voids, and contacts multiple electrically conductive layers (word lines) at different heights. The stepped bottom edges with vertically-extending segments allow a single contact well structure to interface with multiple word lines, eliminating the need for separate contact structures for each layer.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240290714A1Three-dimensional memory device containing multi-level word line contact wells and methods for manufacturing the same
Publication Date: 2024.08.29 SANDISK TECHNOLOGIES LLC
  • US20240290714A1 patent drawing
  • US20240290714A1 patent drawing
  • US20240290714A1 patent drawing

AI summary

A memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings and including a respective memory film and a respective vertical semiconductor channel, contact wells vertically extending through a respective subset of layers of the alternating stack that includes a topmost insulating layer of the insulating layers, dielectric fill structures located in the contact wells, and an array of contact via structures vertically extending through the respective dielectric fill structure in each of the contact wells and contacting a top surface of a respective electrically conductive layer within a subset of the electrically conductive layers, the subset of the electrically conductive layers including a plurality of electrically conductive layers that are vertically spaced apart.