3D Memory Array Layout With Overlying Control Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Microelectronic device designers face challenges in reducing feature dimensions and separation distances to increase integration density while maintaining performance and simplifying fabrication, particularly due to processing conditions affecting control logic devices in memory devices like DRAM.
Innovation Solution
The design incorporates vertical channel access devices and memory cells with a novel configuration that includes a carrier structure, memory array structure, and control circuitry structure, utilizing conductive and insulative materials to reduce horizontal footprint and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control logic devices are provided in electrical communication with digit lines and word lines through routing and contact structures, then memory array functionality is achieved, but processing conditions (temperatures, pressures, materials) limit the configurations and performance of control logic devices
Solution Approach 1:
The patent transitions control logic devices from a planar two-dimensional arrangement to a three-dimensional vertical arrangement. Control logic devices are positioned above the memory array and connected through vertical contact structures, enabling independence from processing condition constraints while maintaining electrical communication with digit lines and word lines.
Solution Approach 2:
The patent separates control logic devices from the memory array structure, placing them in distinct spatial zones. This segmentation allows control logic devices to be formed independently without being constrained by the processing conditions required for memory array fabrication, while still achieving functional integration through vertical interconnect structures.
2Productivity
If quantities, dimensions, and arrangements of control logic devices are increased to improve memory functionality, then memory operations are enhanced, but horizontal footprint of memory device increases
Solution Approach 1:
The patent utilizes the vertical dimension to accommodate control logic devices above the memory array, transforming the layout from a horizontal plane to a three-dimensional structure. This enables multiple control logic devices to be stacked vertically, increasing memory operation capability without expanding the horizontal footprint.
Solution Approach 2:
The patent implements a nested arrangement where control logic devices are positioned above and connected to the memory array through vertical interconnect structures. This nesting approach allows control logic devices to occupy the vertical space above the memory array, effectively utilizing three-dimensional space to enhance functionality while maintaining a compact horizontal footprint.
3Quantity of substance
If feature dimensions and separation distances are reduced to increase integration density, then integration density is improved, but fabrication complexity and processing constraints increase
Solution Approach 1:
The patent achieves high integration density by utilizing the vertical dimension for control logic device placement and interconnect structures. This three-dimensional approach allows features to be separated in the vertical direction rather than requiring further reduction of horizontal dimensions, thereby maintaining fabrication simplicity while increasing integration density.
Data Source
AI summary
A microelectronic device includes a memory array structure, an additional memory array structure, and a control circuitry structure. The memory array structure includes memory cells respectively including a vertical channel access device and a storage node device coupled to the vertical channel access device. The additional memory array structure vertically overlies the memory array structure and includes additional memory cells respectively including an additional vertical channel access device and an additional storage node device coupled to the additional vertical channel access device. The control circuitry structure vertically overlies and is bonded to one or more of the memory array structure and the additional memory array structure. The control circuitry structure includes control logic circuitry coupled to the memory cells of the memory array structure and the additional memory cells of the additional memory array structure. Related memory devices and electronic systems are also described.