3D Memory Array Layout With Vertically Offset Control Logic
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Solution Overview
Problem
Microelectronic device designers face challenges in reducing the size and improving the performance of memory devices, such as DRAM, due to processing conditions and the configuration of control logic devices, which limit the integration density and performance enhancements.
Innovation Solution
The method involves forming microelectronic devices with vertically offset control logic devices within array regions, using specific configurations of array, digit line exit, word line exit, and socket regions, and employing conductive and insulative materials to optimize the arrangement and performance of memory cells and control logic circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If control logic devices are formed using conventional processing conditions, then the memory array can be fabricated, but the integration density and performance are limited due to the horizontal footprint and configuration constraints
Solution Approach 1:
The patent transitions control logic devices from a conventional horizontal planar arrangement to a vertical three-dimensional configuration. Control logic devices are positioned at different vertical levels (first level, second level, third level) above the memory array, enabling increased integration density by utilizing the vertical dimension rather than being constrained to horizontal placement only.
Solution Approach 2:
The control logic devices are divided into multiple segmented units distributed across different vertical levels. Each control logic device is positioned at a specific vertical level (first, second, or third level) and horizontally between adjacent memory cells, creating a segmented hierarchical structure that improves both density and performance.
2Area of stationary object
If the horizontal footprint of control logic devices is reduced, then integration density improves, but performance (speed, power consumption) deteriorates due to smaller dimensions
Solution Approach 1:
The patent resolves this contradiction by moving control logic devices to the vertical dimension. Devices at higher vertical levels can maintain adequate horizontal dimensions for performance while occupying minimal horizontal footprint space, as their primary placement is in the vertical direction above the memory array rather than expanding horizontally.
Solution Approach 2:
Different regions of the device structure are assigned different functions at different vertical levels. Control logic devices at specific vertical levels perform specific control functions, allowing optimization of local device dimensions and performance characteristics while maintaining overall high integration density through vertical stacking.
Data Source
AI summary
A method of forming a microelectronic device comprises forming a microelectronic device structure comprising memory cells, digit lines, word lines, and at least one isolation material covering and surrounding the memory cells, the digit lines, and the word lines. An additional microelectronic device structure comprising control logic devices and at least one additional isolation material covering and surrounding the control logic devices is formed. The additional microelectronic device structure is attached to the microelectronic device structure. Contact structures are formed to extend through the at least one isolation material and the at least one additional isolation material. Some of the contact structures are coupled to some of the digit lines and some of the control logic devices. Some other of the contact structures are coupled to some of the word lines and some other of the control logic devices. Microelectronic devices, electronic systems, and additional methods are also described.