3D Memory Array Stacking With Separate Control Logic Formation
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Solution Overview
Problem
Microelectronic device designers face challenges in increasing memory density and performance while reducing the size and fabrication costs of memory devices, particularly due to processing conditions and the configuration of control logic devices within the base control logic structure of 3D memory arrays.
Innovation Solution
The method involves forming a microelectronic device structure with a base structure, a doped semiconductive material, and a stack structure with alternating conductive and insulative layers, cell pillar structures extending through the stack and base, and digit line structures, which are integrated with control logic devices to enhance memory array performance and reduce size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processing conditions (temperatures, pressures, materials) are optimized for memory array formation, then memory array performance is improved, but control logic device configurations and performance are limited
Solution Approach 1:
The patent divides the device into two separately formed structures: a memory array structure formed first under specific processing conditions, and a control logic structure formed later under different processing conditions. This segmentation allows each structure to be optimized independently, resolving the contradiction between memory array performance and control logic device adaptability.
Solution Approach 2:
The memory array structure is formed in advance before the control logic structure. This preliminary action allows the memory array to be optimized for its specific performance requirements, while subsequent formation of the control logic structure allows for greater configurational flexibility without compromising the already-optimized memory array.
2Reliability
If quantities, dimensions, and arrangements of control logic devices are increased to improve functionality, then device performance is enhanced, but device size (horizontal footprint) increases
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked architecture where control logic devices are positioned vertically above the memory array. This dimensional change allows increased device functionality and performance without proportionally increasing the horizontal footprint, as the additional components occupy vertical space rather than lateral space.
3Quantity of substance
If conventional vertical memory array architectures are used to increase memory density, then more memory cells fit in unit die area, but fabrication complexity increases
Solution Approach 1:
The patent segments the fabrication process into distinct stages: first forming the memory array structure, then forming the control logic structure separately. This segmentation simplifies the overall fabrication complexity by allowing each structure to be optimized for its specific manufacturing requirements, rather than attempting to fabricate both simultaneously under conflicting constraints.
Data Source
AI summary
A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.