3D Memory Structure Layout for Copper BEOL Thermal Stability
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Solution Overview
Problem
The fabrication of 3D NAND memory structures faces challenges such as high anneal temperatures causing metallization layer shifts and the need for high aspect ratio vias, which increase complexity and cost, and the limitations of using copper interconnects due to these conditions.
Innovation Solution
A 3D memory structure and method involving a substrate with a memory array stack, a far-back-end-of-the-line (FBEOL) structure, and a back-end-of-the-line (BEOL) structure, where the memory array stack is annealed before forming the FBEOL, allowing copper interconnects in the BEOL, and through-silicon vias connect the FBEOL and BEOL structures, reducing thermal issues and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high anneal temperatures are used to form the memory array stack, then the memory structure achieves proper crystal orientation and material properties, but metallization layers shift and deformation occurs
Solution Approach 1:
The memory array stack is annealed before forming the FBEOL metallization layers, so that the high-temperature processing is completed before any metallization is deposited. This preliminary action ensures that subsequent metallization layers are not exposed to thermal stress that would cause shifting or deformation.
2Power
If copper interconnects are used in the BEOL structure, then electrical conductivity is improved, but thermal issues arise during high temperature annealing
Solution Approach 1:
The memory array stack annealing is performed before forming the copper interconnects in the BEOL structure. By completing the high-temperature annealing process first, the copper interconnects are not exposed to temperatures that would cause thermal degradation, thereby maintaining both electrical conductivity and thermal stability.
3Reliability
If high aspect ratio vias are formed to connect FBEOL and BEOL structures, then electrical connectivity is achieved, but fabrication complexity and cost increase
Solution Approach 1:
The memory array stack is annealed before forming the FBEOL structure and subsequent vias. This sequencing allows for more manageable via formation processes rather than requiring extremely high aspect ratio vias through already-formed complex structures, thereby reducing fabrication complexity while maintaining electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables stable copper interconnects in the BEOL structure, avoids metallization layer shifts, and simplifies the fabrication process by annealing the memory array stack before forming the FBEOL, improving the thermal budget and reducing the complexity of high aspect ratio via formation.
Implementation Method 1
the memory array stack is annealed before forming the FBEOL
Data Source
AI summary
A three-dimensional (3D) memory structure includes a memory array formed on a side of a substrate, a far-back-end-of-line (FBEOL) structure formed on the memory array, and a back-end-of-line (BEOL) structure formed on another side of the substrate opposite the side on which the memory array and the BEOL structure are formed. Methodologies to fabricate the 3D memory structure are also disclosed and include forming the memory array on the substrate, forming the FBEOL on the memory array, flipping the substrate, and forming the BEOL on the opposite side of the substrate. Alternative 3D memory structures and fabrication methodologies are also disclosed.