3D Memory Source Line Resistance via Corrugated Contact Via
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Solution Overview
Problem
Three-dimensional memory devices face challenges in achieving low source line resistance, which affects their performance and efficiency.
Innovation Solution
The solution involves forming a three-dimensional memory device with a specific structure that includes an alternating stack of insulating and conductive layers over a substrate, a memory stack structure with a semiconductor channel layer, and a source contact via structure with a corrugated bottom surface to reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional source contact via structure is used, then the device structure is simple, but the source line resistance is high
Solution Approach 1:
The patent transitions from a conventional planar contact interface to a three-dimensional corrugated interface. The bottom surface of the source contact via structure is formed with raised and recessed portions, creating a multi-dimensional contact geometry that increases the effective contact area with the source region without expanding the device footprint in the planar direction.
Solution Approach 2:
The patent employs curved and undulating surfaces in the contact via structure. The corrugated bottom surface features raised and recessed portions with curved transitions, maximizing the interfacial contact area between the conductive via structure and the source region. This curved geometry provides superior electrical contact compared to flat interfaces.
2Reliability
If the contact area between source region and via structure is increased, then the source line resistance decreases, but the manufacturing complexity increases
Solution Approach 1:
The corrugated bottom surface pattern is established in the source contact via structure before final fill and planarization steps. By pre-forming the raised and recessed portion pattern in earlier fabrication stages, the complex three-dimensional contact geometry is created while simplifying subsequent processing steps.
Solution Approach 2:
The patent replaces complex mechanical patterning techniques with deposition and etching-based approaches. The corrugated structure is formed through conformal deposition of conductive materials followed by anisotropic etching, substituting mechanical fabrication methods with vapor-phase processes that achieve superior surface coverage and pattern fidelity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces source line resistance, enhancing the performance and efficiency of the memory devices by increasing the interface area between the source regions and the contact via structure, thereby improving on-current and allowing for a more compact device design.
Implementation Method 1
having a corrugated bottom surface including raised horizontal bottom surface portions and recessed horizontal bottom surface portions adjoined by interconnecting sidewall surfaces
Implementation Method 2
Physically exposed regions of the semiconductor channel layer underneath the backside trench are converted into source regions by introducing electrical dopants therein
Data Source
AI summary
Dielectric pedestal structures embedded in a sacrificial material layer is formed between a substrate and an alternating stack of insulating layers and spacer material layers. After memory openings are formed through the alternating layer, a cavity is formed by removal of the sacrificial material layer selective to the dielectric pedestal structures. A memory film, a semiconductor channel layer, and a dielectric core are sequentially formed in the volume including the cavity and the memory openings. A backside trench is formed through the alternating stack in an area that straddles the dielectric pedestal structures. By recessing the dielectric pedestal structures selective to the semiconductor channel layer, planar regions and vertical regions of the semiconductor channel layer can be physically exposed, which are converted into source regions. Contact resistance can be lowered due the increased contact area provided by vertical source portions.