3D Vertical Memory Array Layout for Dense Cross-Point Cells

The patent transitions from two-dimensional planar memory architecture to three-dimensional vertical architecture by stacking multiple memory cell layers vertically. This is achieved by forming alternating layers of conductive material and insulative material, then creating vertical pillars that penetrate through multiple layers to form memory cells at three-dimensional crosspoints, thereby increasing storage capacity per unit area.

The memory array is segmented into multiple stacked layers, with each layer containing alternating conductive and insulative material layers. Vertical pillars are segmented to intersect with horizontal word lines at multiple levels, creating discrete memory cells at each crosspoint. This segmentation enables independent addressing and manipulation of individual cells within the three-dimensional structure.

The patent employs thin film deposition techniques to create uniformly thick layers of conductive and insulative materials with precise thickness control. The insulative material layers act as spacers that define the spacing between adjacent conductive layers, while the conformal deposition process ensures uniform spacing throughout the three-dimensional structure, reducing variability in cell dimensions.

The patent controls the thickness parameters of alternating conductive and insulative layers to optimize cell density while maintaining manufacturability. By adjusting the thickness of insulative spacer layers and conductive pillar diameters, the design achieves reduced cell spacing while keeping manufacturing precision requirements within feasible limits through parameter optimization.

The patent implements self-selecting memory cells where the intersection of a selected word line and digit line automatically activates the memory cell at their crosspoint without requiring additional selection transistors. This self-selecting mechanism reduces the number of active components per cell, lowering power consumption while maintaining fast access speeds through direct resistive switching of the chalcogenide storage element.

The patent replaces traditional transistor-based cell selection mechanisms with direct electrical resistance switching in chalcogenide materials. The storage element itself serves as the switching mechanism, eliminating the need for additional access transistors and reducing both power consumption and access time by using electrical field effects rather than mechanical or complex electronic switching.