3D Memory Array Layout for Crosstalk-Resistant Vertical Stacking
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Solution Overview
Problem
Three-dimensional memory arrays face issues of crosstalk between adjacent storage bits, leading to increased power consumption, reduced read-write speed, complex wiring, and reduced effective area, which affect device performance.
Innovation Solution
A three-dimensional memory array design with memory cells stacked vertically, where transistors and storage nodes are connected in series and parallel configurations, and word lines and bit lines are arranged to minimize crosstalk, allowing for simple wiring and maximum vertical stacking density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory structure is adopted to increase integration density, then memory capacity is improved, but crosstalk between adjacent storage bits increases
Solution Approach 1:
The memory array is divided into multiple independent memory blocks (MB0, MB1, MB2, etc.) separated by isolation structures. Each memory block contains independently controllable memory cells, allowing selective activation of specific blocks during read/write operations. This segmentation isolates adjacent storage bits from each other, preventing crosstalk while maintaining high memory capacity through vertical stacking.
Solution Approach 2:
Isolation structures (such as dielectric layers or isolation trenches) are introduced as intermediary elements between adjacent memory blocks and storage bits. These isolation structures act as mediators that electrically and physically separate adjacent storage bits, blocking the harmful crosstalk signals while allowing the memory structure to maintain its three-dimensional high-density configuration.
2Quantity of substance
If three-dimensional memory structure is adopted to increase integration density, then memory capacity is improved, but power consumption increases
Solution Approach 1:
The memory array is segmented into multiple independent memory blocks that can be selectively activated. During read/write operations, only the specific memory block containing the target storage bit is activated, while other blocks remain in a low-power state. This selective activation significantly reduces overall power consumption compared to activating the entire memory array, enabling high memory capacity with lower power usage.
Solution Approach 2:
The memory structure enables periodic or selective activation of different memory blocks based on access patterns. By activating only the necessary memory blocks during specific time periods and keeping others inactive, the system reduces average power consumption while maintaining high memory capacity through the stacked three-dimensional architecture.
3Quantity of substance
If three-dimensional memory structure is adopted to increase integration density, then memory capacity is improved, but read-write speed is reduced
Solution Approach 1:
The memory array is divided into multiple independent memory blocks with independent word lines and bit lines for each block. This segmentation enables parallel access to different memory blocks simultaneously, allowing multiple read/write operations to occur in parallel. The isolation structures ensure that operations in one block do not interfere with others, maintaining high read-write speed while achieving high memory capacity through vertical stacking.
Solution Approach 2:
The patent transitions from two-dimensional planar memory to three-dimensional stacked memory by adding the vertical dimension. Memory cells are stacked vertically along the Z-axis, creating multiple layers of memory blocks. This dimensional change increases memory capacity without proportionally increasing the footprint area, and the isolated block structure within each layer maintains fast read-write speeds by enabling independent parallel operations.
4Quantity of substance
If three-dimensional memory structure is adopted to increase integration density, then memory capacity is improved, but wiring complexity increases
Solution Approach 1:
The memory array is segmented into multiple independent memory blocks, each with its own isolated set of word lines and bit lines. The isolation structures physically separate the wiring of adjacent blocks, preventing signal interference and simplifying the wiring design. Each block can be independently addressed and controlled, reducing the overall wiring complexity compared to a monolithic three-dimensional structure where all cells would require interconnected wiring.
Solution Approach 2:
The patent utilizes the vertical dimension to stack multiple memory blocks, reducing the horizontal wiring complexity. By arranging memory cells vertically along the Z-axis, the word lines and bit lines can be organized in a more systematic manner across layers, with isolation structures managing the wiring between blocks. This three-dimensional organization simplifies the overall wiring architecture compared to expanding memory capacity through horizontal planar expansion.
5Quantity of substance
If three-dimensional memory structure is adopted to increase integration density, then memory capacity is improved, but effective area of memory array is reduced
Solution Approach 1:
The patent transitions from two-dimensional planar memory to three-dimensional stacked memory by adding the vertical dimension. Multiple memory blocks are stacked vertically along the Z-axis, increasing memory capacity without proportionally increasing the horizontal footprint area. The isolation structures enable this vertical stacking by providing electrical and physical separation between blocks, allowing the memory array to achieve high capacity while maintaining a compact effective area.
Solution Approach 2:
The memory array is segmented into multiple independent memory blocks that can be vertically stacked. Each block is isolated by separation structures, allowing efficient space utilization through vertical arrangement. This segmentation enables the memory system to achieve high integration density by stacking blocks in the vertical dimension rather than expanding horizontally, thereby improving memory capacity while preserving effective area.
Data Source
AI summary
A three-dimensional memory array includes a first memory cell array including a plurality of memory cells stacked along a vertical direction, a plurality of word lines, and at least one bit line. Each memory cell includes a transistor and a storage node coupled in a horizontal direction and connected in parallel to each other. The transistors in the plurality of memory cells, and/or the storage nodes in the plurality of memory cells in the vertical direction are connected in series to each other. The plurality of word lines are spaced apart along the vertical direction and connected to the transistors in the plurality of memory cells in the vertical direction, respectively. The bit line extends along the vertical direction and is connected to the transistors in the plurality of memory cells in the vertical direction.