3D Memory Capacitor Structure Above CUA for Higher Die Density
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Solution Overview
Problem
In the development of 3D NAND memory devices, there is a challenge in optimizing the use of space within the memory die to increase memory capacity while minimizing the circuit area, as existing designs often require additional space for capacitors and control circuitry, leading to inefficiencies in memory density and area utilization.
Innovation Solution
The implementation of a capacitor structure within the spare 3D space adjacent to the memory array, utilizing conductive structures separated by dielectric material to form a capacitor that can be coupled to control circuitry below the memory array, thereby avoiding the need for additional die area and enhancing memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitors are placed in traditional locations within the memory die, then they can provide necessary capacitance for control circuitry, but they occupy additional die area that reduces memory density
Solution Approach 1:
The patent places capacitors in the third dimension by locating them in the inter-tier spacing above the control circuitry rather than in the planar die area. This vertical placement in the z-dimension allows capacitance to be provided without consuming additional horizontal die area, effectively resolving the contradiction between capacitance quantity and die area.
Solution Approach 2:
The capacitor structures are nested within the existing 3D memory architecture by utilizing the inter-tier spacing that already exists above the control circuitry. This nesting approach allows capacitors to be integrated into the existing structure without requiring additional die area, as they occupy the vertical space between memory tiers.
2Quantity of substance
If memory density is increased by reducing circuit area, then more memory cells can be packed into the die, but space for necessary components like capacitors becomes limited
Solution Approach 1:
By moving capacitor placement to the vertical dimension (inter-tier spacing above control circuitry), the patent frees up horizontal die area for additional memory cells while maintaining the necessary space for capacitor components in the z-dimension. This enables increased memory density without sacrificing component placement capability.
Solution Approach 2:
The inter-tier spacing, which is already present in the 3D memory structure for other purposes, is utilized to house the capacitor structures. This self-service approach allows the existing architectural feature to serve dual purposes: maintaining memory tier separation and providing space for capacitors, thereby preserving component space while maximizing memory density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased capacitance and efficient use of space, enabling higher memory densities without expanding the circuit area, thus addressing the limitations of existing designs by integrating capacitors in previously unused space above the control circuitry.
Implementation Method 1
The conductive structures separated by dielectric material and arranged to form a capacitor coupled between nodes configured to provide different voltages
Data Source
AI summary
Memory devices can be structured in a three-dimensional arrangement using a circuit under array (CUA) architecture. The memory array of such a memory device can include memory cells disposed in vertically arranged tiers. With the memory array extending over a substrate, the CUA region under the memory array can include control circuitry for the memory array. A space adjacent the memory array and disposed above the CUA region can include a dielectric material and conductive structures, with the conductive structures extending vertically in the dielectric material and alongside the memory array. The conductive structures separated by the dielectric material can be used as a capacitor coupled between nodes with the nodes configured to provide different voltages. This capacitor can be coupled to a circuit or a connection node below the level of the memory array.