3D Memory Read Circuit Using Current Comparison for Fast Access
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Solution Overview
Problem
In memory devices with a large number of memory cells connected to a bit line, access time is increased, and power consumption is higher when using current sensing amplifiers compared to voltage sensing amplifiers, while circuit area is not optimized.
Innovation Solution
A memory device structure with a reading circuit and memory cells, where transistors in the reading circuit and memory cells include silicon and metal oxide in the channel formation region, allowing current-based data reading with reduced power consumption and circuit area through specific transistor connections and configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large number of memory cells are electrically connected to one bit line, then storage capacity per unit area is increased, but access time is increased
Solution Approach 1:
The patent transitions from planar memory cell arrangement to three-dimensional stacking of memory cells. Multiple memory cell layers are stacked vertically with bit lines extending through the stack, enabling high storage capacity while maintaining short bit line lengths and fast access times.
Solution Approach 2:
The memory device is divided into multiple stacked memory cell layers, each layer containing a subset of memory cells connected to the bit line. This segmentation allows parallel access to different layers, reducing overall access time while increasing total storage capacity.
2Loss of time
If a current sensing amplifier is used for data reading, then access time is shortened, but power consumption is increased
Solution Approach 1:
Instead of using a full current sensing amplifier for all memory cells, the patent employs a simplified sensing circuit that performs partial sensing operations. The sensing amplifier processes only the necessary current signals from the stacked memory cells, reducing power consumption while maintaining fast access times.
3Loss of time
If a current sensing amplifier is used for data reading, then access time is shortened, but circuit area is increased
Solution Approach 1:
The patent moves the sensing circuitry into the third dimension by stacking memory cells vertically around the bit line. This three-dimensional configuration reduces the horizontal circuit area required for sensing amplifiers while maintaining fast access capabilities.
Solution Approach 2:
The patent integrates the sensing amplifier circuitry with the stacked memory cell structure, merging multiple functions into a compact three-dimensional arrangement. This reduces the overall circuit area compared to traditional planar configurations.
Data Source
AI summary
A memory device with shortened access time in data reading is provided. The memory device includes a first layer and a second layer positioned above the first layer, the first layer includes a reading circuit, and the second layer includes a first memory cell and a second memory cell. The reading circuit includes a Si transistor. The first memory cell and the second memory cell each include an OS transistor. The first memory cell is electrically connected to the reading circuit, and the second memory cell is electrically connected to the reading circuit. When a first current corresponding to first data retained in the first memory cell flows from the reading circuit to the first memory cell and a second current corresponding to second data retained in the second memory cell flows from the reading circuit to the second memory cell, the reading circuit compares the current amounts of the first current and the second current, and reads the first data.