3D Memory Channel Structure With Cut Ring Layer for Reliability
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and improving electrical characteristics and reliability, particularly in three-dimensional memory cell arrangements.
Innovation Solution
A semiconductor device with a stack structure featuring interlayer insulating layers, gate electrodes, separation patterns, and channel structures, including a cutting channel structure with a ring-shaped channel layer and a second separation pattern, enhancing electrical connectivity and reliability through specific layer arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used instead of two-dimensionally arranged memory cells, then data storage capacity is increased, but electrical characteristics and reliability deteriorate
Solution Approach 1:
The patent divides the three-dimensional memory structure into multiple independent channel structures (first channel structure and second channel structure) with separate gate dielectric layers. Each channel structure has its own tunneling layer, data storage layer, and blocking layer, allowing independent electrical control and preventing interference between adjacent memory cells, thus maintaining reliability while achieving high storage capacity
Solution Approach 2:
The patent applies different structural configurations to different channel structures within the same three-dimensional memory device. Specifically, the second channel structure has its channel layer end portions recessed relative to the data storage layer end portions, creating localized structural variations that optimize electrical characteristics for specific regions while maintaining overall high storage capacity
2Reliability
If channel layer end portions are recessed relative to data storage layer end portions, then electrical characteristics are improved, but manufacturing complexity increases
Solution Approach 1:
The patent resolves the manufacturing complexity issue by addressing the dimensional relationship between channel layer and data storage layer in the vertical dimension rather than requiring complex lateral positioning. The recessed configuration is achieved through sequential deposition and etching processes that work in the vertical direction, simplifying manufacturing while maintaining the electrical benefits of the recessed structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances data storage capacity and improves electrical characteristics and reliability by optimizing the structural arrangement of gate electrodes and channel structures, facilitating efficient electron tunneling and data storage operations.
Implementation Method 1
The first gate dielectric layer includes a first tunneling layer, a first data storage layer, and a first blocking layer, sequentially arranged from the outer side surface of the first channel layer toward the plurality of gate electrodes
Data Source
AI summary
A semiconductor device includes a stack structure, first separation patterns passing through the stack structure, a second separation pattern passing through at least a portion of the stack structure between the first separation patterns, and a cutting channel structure passing through the stack structure and having an end portion partially cut by the second separation pattern. A channel layer of the cutting channel structure has a ring shape cut by the second separation pattern to have end portions of the channel layer which are spaced apart from each other.