3D NAND Memory Stack With Dam Structure for Reliability
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in increasing data storage capacity while maintaining performance and reliability.
Innovation Solution
A semiconductor memory device with a three-dimensional arrangement of memory cells, featuring a stacked structure of gate electrodes, channel structures, and dam structures, which include interlayer insulating layers and capping insulating layers to enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking, where multiple gate electrodes are stacked in the vertical direction (first direction perpendicular to substrate) to form a stacked structure. This dimensional change enables increased storage capacity by utilizing the vertical space above the substrate rather than only the planar area.
Solution Approach 2:
The memory device is segmented into distinct functional components: a substrate, multiple gate electrodes stacked vertically, channel structures extending through the stack, and dam structures surrounding portions of the stacked structure. This segmentation allows each component to be optimized independently while maintaining overall system functionality and manageability.
2Productivity
If gate electrodes are stacked vertically to increase integration, then integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements a nested structure where multiple gate electrodes are stacked vertically within a confined space above the substrate. Each gate electrode is positioned at a different height, creating a nested arrangement that maximizes integration density. The dam structures further nest around portions of this stacked structure, providing structural support and definition.
Solution Approach 2:
The dam structures are positioned to surround only specific portions of the stacked structure rather than the entire structure, allowing different regions to have different structural characteristics. This local quality approach enables selective reinforcement where needed while maintaining manufacturing feasibility.
3Reliability
If dam structures are added to surround the stacked structure, then reliability is improved, but device complexity increases
Solution Approach 1:
The dam structures are positioned to surround portions of the stacked structure in advance, providing structural support and protection before the device undergoes operational stress. This beforehand cushioning approach prevents potential failures by reinforcing the structure proactively, thereby improving reliability.
Data Source
AI summary
There is provided a semiconductor memory device that has improved performance and/or reliability. The semiconductor memory device includes a substrate, a stacked structure including a plurality of gate electrodes stacked on the substrate and spaced apart from each other in a first direction, the first direction being perpendicular to an upper surface of the substrate, a channel structure extending in the first direction and crossing the plurality of gate electrodes, and a dam structure extending in the first direction and surrounding at least a portion of the stacked structure in a plan view, on the substrate. A height of an upper surface of the dam structure from the upper surface of the substrate is lower than a height of the channel structure from the upper surface of the substrate.