3D Memory Cell Architecture With Multi-Level Data Line Layout
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Solution Overview
Problem
The manufacturing of three-dimensional (3D) memory devices poses challenges due to the complexity of fabrication processes, which can affect the efficiency and reliability of these devices.
Innovation Solution
The development of a memory device architecture where memory cells are arranged in multiple device levels, with data lines located either below or above the memory cells, allowing for efficient read and write operations and enabling global erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in multiple device levels with data lines located below or above the memory cells, then storage density and operational efficiency are improved, but fabrication process complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking with multiple device levels. Memory cells are arranged in vertical columns extending through multiple device levels, with data lines positioned either below or above the memory cell arrays. This dimensional change increases storage density by utilizing vertical space while maintaining manufacturability through systematic fabrication processes.
2Quantity of substance
If conventional 3D memory device fabrication processes are used, then storage density can be increased, but manufacturing reliability decreases due to process complexity
Solution Approach 1:
The fabrication process is divided into distinct sequential stages: forming insulating layers, forming conductive layers, creating memory cell structures at different device levels, and positioning data lines. Each stage is independently optimized and controlled, which reduces process variability and improves manufacturing reliability while achieving high storage density through the multi-level vertical architecture.
3Ease of operation
If data lines are located below memory cells, then read and write operations are facilitated, but fabrication complexity increases
Solution Approach 1:
The patent describes a universal fabrication methodology that can accommodate both configurations: data lines positioned below memory cells or data lines positioned above memory cells. The same fundamental fabrication processes and structural approaches are used regardless of data line position, allowing optimization for specific application requirements without developing entirely separate manufacturing processes.
Data Source
AI summary
Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.